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ps034404-0417 preliminary copyright ?2017 zilog ? , inc. all rights reserved. www.zilog.com product specification zneo32! cortex-m3 z32f0641 mcu
ps034404-0417 p r e l i m i n a r y z32f0641 mcu product specification ii do not use this product in life support systems. life support policy zilog?s products are not authorized for use as critical components in life support devices or systems without th e express prior written approval of the president and general counsel of zilog corporation. as used herein life support devices or systems are devices which (a) ar e intended for surgical impl ant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a signi ficant injury to the user. a criti- cal component is any component in a life support device or system whose failure to perform can be reason- ably expected to cause the failure of the life support devi ce or system or to affect its safety or effectiveness. document disclaimer ?2017 zilog, inc. all rights reserved . information in this pu blication concerning the devices, applications, or technology described is intend ed to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. the information contained w ithin this document has been verified according to the general principles of electrical and mechanical engineering. zneo32! is a trademark or registered trademark of z ilog, inc. all other product or service names are the property of their respective owners. warning:
ps034404-0417 p r e l i m i n a r y revision history z32f0641 mcu product specification iii revision history each instance in this document?s revision history reflects a change from its previous edi- tion. for more details, refer to the corresponding page(s) or appropriate links furnished in the table below. date revision level description page apr 2017 04 updated part numbers to include the cortex m identifier. all aor 2016 03 added timing information for periph erals; global edits for clarity. all feb 2016 02 updated figure 18.2 lqfp-32 package dimension. 178 nov 2015 01 original issue.
z32f064 1 product specification overview ps03440 4 - 0417 preliminary 1 1. overview i ntroduction zilogs z32f064 1 mcu, a member of the zneo32! family of microcontrollers, is a cost - effective and high - performance 32 - bit microcontroller. the z32f064 1 mcu provides a 3 - phase pwm generator unit which is suitable for inverter bridges, i n cluding motor drive systems. two 12 - bit high speed adc units with 16 - channel analog multiplexed inputs support feedback retrieval from the inverter bridge. multiple p owerful external serial interface s help communicate with on - board sensors and devices. figure 1 . 1 shows a block diagram of the z32f064 1 mcu. figure 1 . 1 block diagram
z32f064 1 product specification overview ps03440 4 - 0417 preliminary 2 figure 1 . 2 and figure 1 . 3 show the pin layouts . figure 1 . 2 pin l ayout ( l qfp - 48 )
z32f064 1 product specification overview ps03440 4 - 0417 preliminary 3 figure 1 . 3 pin l ayout ( lqfp - 32 )
z32f064 1 product specification overview ps03440 4 - 0417 preliminary 4 product features the z32f064 1 mcu offers t he following features : ? high performance l ow - power cortex - m3 c ore ? 64 kb c ode flash m emory with c ache function ? 8 kb sram ? 3 - phase pwm with adc triggering function ? 1 .5 msps high - speed adc with sequential conversion function o 2 u nits with 1 1 c hannel i nput s ? watchd og t imer ? six g eneral p urpose t imers o periodic, one - shot, pwm, capture mode o multi - t imer s ynchronization o ption ? external communication ports : o 2 uarts o 1 i 2 c o 1 spi ? direct memory access (dma) controller with 4 channels ? system f ail - safe function by c lock m onito ring ? xtal osc f ail monitoring ? debug and e mergency stop function ? s erial w ire d ebug (swd) and jtag debugger ( jtag is only for lqfp - 48) ? supports uart and spi isp ? two types of p ackage options o l qfp - 48 (0.5mm pitch) o l qfp - 32 (0.65mm pitch) ? industrial grade opera ting temperature ( - 40 ~ + 8 5 ) table 1 . 1 device t ype part number flash sram uart spi i2c mpwm adc i/o p orts p ackage z32f06410aes 64kb 8kb 2 1 1 1 2 - unit 11 ch 44 lqfp - 48 Z32F06410AKS 64kb 8kb 2 1 1 1 2 - unit 8 ch 30 lqfp - 32
z32f064 1 product specification overv iew ps03440 4 - 0417 preliminary 5 a rchit ecture block diagram a n internal block diagram of the z32f064 1 mcu is shown in figure 1 . 4 . figure 1 . 4 internal block diagram debug cortex - m3 (max. 48mhz) advanced high - performance bus (ahb) matrix sram (8kb) advanced perip h - eral bus (apb) nvic spi x 1 i2c x 1 16 - bit wdt 16 - bit timer x 6 scu vdc lvd mainosc ringosc pll por jtags wd pd pa pb pc uart x 2 1.5msps 12 - bit adc 11 ch nmi code flash (64kb) dmac
z32f064 1 product specification overview ps03440 4 - 0417 preliminary 6 functional description the following section provides an overview of the features of the z32f064 1 microcontroller. arm cortex - m3 ? arm - powered cortex - m3 c ore based on armv7m architecture , which is optimized for small - size and low - power system s . on core system timer (systick) provides a simple 24 - bit timer that enables easy management of system operation s ? thumb - compatible thumb - 2 only instruction set processor core makes code high - density ? hardware division a nd single - cycle multiplication ? integrated nested vectored interrupt controller (nvic) provides deterministic interrupt handling ? jtag and swd debugging features ? max imum 48 mhz operating frequency with zero wait execution nested vector - interrupt controller (nvic) ? the arm nested vectored interrupt controller (nvic) on the arm cortex - m3 core handles all internal and external e xceptions. when an interrupt condition is detected, the processor state is automatically stored to the stack and automatically restored from the stack at the end of interrupt service routine. ? the vector is fetched in parallel to the state saving, which ena bles efficient interrupt entry. ? the processor supports tail - chaining , which allows for back - to - back interrupts to be performed without the overhead of state sav ing and restoring 64 kb internal code flash memory ? the z32f064 1 mcu provides internal 64 kb code f lash memory and its controller , w hich is sufficient to program the motor algorithm and control the system. self - programming is available and isp and jtag programming is also supported in boot or debugging mode. ? instruction and data cache buffer are presen t and overcome the low - bandwidth flash memory. the cpu can execute from flash memory with zero wait state up to 48 mhz bus frequency. 8 kb 0 - wait internal sram ? on chip 8 kb 0 - wait sram can be used for working memory space and program code can be loaded on this sram boot logic ? s mart boot logic supports f lash programming . the z32f064 1 mcu can be accessed by an external boot pin ; uart and spi programming are available in b oot m ode system control unit ? the system control unit ( scu ) block manages internal power, c lock, reset , and o peration m ode. the scu also controls analog blocks (o scillator block , vdc and lvd ) 32 - bit watchdog timer ? t he watchdog timer (wdt) performs the system monitoring function. the wdt generate s an internal reset or interrupt if the system is i n abnormal stat e multi - purpose 16 - bit timer ? six - c hannel 16 - bit general purpose timer s support the following functions o periodic timer mode o counter mode o pwm mode o capture mode
z32f064 1 product specification overview ps03440 4 - 0417 preliminary 7 ? built - in timer also supports counter - synchronization mode which can generat e synch ronized waves and timing motor pwm generator ? 3 - phase motor pwm g enerator is implemented. 16 - bit up/down counter with prescaler supports triangular and saw tooth waveform s ? pwm has the ability to generate internal adc trigger signal s to measure the signal on time ? dead time insertion and emergency stop functionality provide overcurrent protection for the chip and system serial peripheral interface (spi) ? the serial peripheral interface (spi) block provides s ynchronous serial communication. the z32f064 1 mcu has 1 channel spi module which includes the dma function supported by a dma controller. transfer data is moved to/from the memory area without cpu operation ? boot m ode uses this spi block to download the f lash program inter - integrated circuit interface ? the z32f0 64 1 mcu has 1 channel inter - integrated circuit ( i 2 c ) block which support s up to 400 k hz i 2 c communication. m aster and slave m ode s are supported universal as ynchronous receiver/transmitter ? the z32f064 1 mcu has 2 channels universal asynchronous receiver / transm itter ( uar t ) block. for accurate baud rate control, the fractional baud rate generator is provided ? the uart features the dma function , supported by a dma controller. transfer data is moved to/from the m emory area without cpu operation general port i / os ? 16 - bit pa, pb, pc, and pd ports are available and provide multiple functionality : o general i / o port o independent bit set/clear function o external interrupt input port ? programmable pull - up and open - drain selection ? on - chip input d ebounce f ilter 12 - bit analog - to - di gital converter (adc) ? 2 built - in analog - to - digital converters ( adc ) can convert analog signal s up to 1 .5 msps conversion rate. 1 1 - channel analog mux provides various combinations from external analog signals. ? the adc features the dma function, supported by a dma controller. transfer data is moved to/from the me mory area without cpu operation.
z32f064 1 product specification overview ps03440 4 - 0417 preliminary 8 pin description p in configuration s are listed in table 1 . 2 . table 1 . 2 pin description pin n ame pin name type description remark lqfp48 lqfp32 1 1 pa0* ious port a bit 0 input/output an0 ia analog input 0 2 2 pa1* ious port a bit 1 input/output an1 ia analog input1 3 3 pa2* ious port a bit 2 input/output wdto o watchdog ti mer overflow output an2 ia comparator 2 input 4 4 pa3* ious port a bit 3 input/output an3 ia analog input 3 5 - pa4* ious port a bit 4 input/output ss1 i/o slave select 1 for spi0 an4 ia analog input 4 6 - pa5* ious port a bit 5 input /output ss2 i/o slave select 2 for spi0 an5 ia analog input 5 7 5 pa6* ious port a bit 6 input/output t0io i/o timer 0 input/output t2io i/o timer 2 input/output an6 ia analog input 6 8 6 pa7* ious port a bit 7 input/output t1io i/o timer 1 input/output t3io i/o timer 3 input/output an7 ia analog input 7 9 7 pa8* ious port a bit 8 input/output t2io i/o timer 2 input/output t0io i/o timer 0 input/output an8 ia analog input 8 10 - pa9* ious port a bit 9 inpu t/output t3io i/o timer 3 input/output t1io i/o timer 1 input/output an9 ia analog input 9 11 - pa10* ious port a bit 10 input/output ss3 output etm trace data 1 an10 ia analog input 10 12 8 vdd p vdd 13 9 gnd p ground 14 - pa11 * ious port a bit 11 input/output 15 - pa12* ious port a bit 12 input/output t0io i/o timer 0 input/output
z32f064 1 product specification overview ps03440 4 - 0417 preliminary 9 16 - pa13* ious port a bit 13 input/output t1io i/o timer 1 input/output 17 - pa14* ious port a bit 14 input/outpu t t2io i/o timer 2 input/output 18 - pa15* ious port a bit 15 input/output t3io i/o timer 3 input/output 19 10 pb0 ious port b bit 0 input/output pwm0u h output pwm0 u h output 20 11 pb1 ious port b bit 1 input/output pwm0 ul output pwm0 u l output 21 12 pb2 ious port b bit 0 input/output pwm0 v h output pwm0 v h output 22 13 pb3 ious port b bit 1 input/output pwm0 v l output pwm0 v l output 23 14 pb4 ious port b bit 4 input/output pwm0 w h output pwm0 w h output 2 4 15 pb5 ious port b bit 5 input/output pwm0 w l output pwm0 w l output 25 16 pb6 ious port b bit 6 input/output prtin0 input pwm0 protection input signal 0 t0io i/o timer 0 input/output 26 17 pb7 ious port b bit 7 input/output ovin0 input pwm0 over - voltage input signal 0 t1io i/o timer 1 input/output 27 18 pc0 ious port c bit 0 input/output t ck/sw c k input jtag tck, swd clock input rxd1 input uart0 rx data input 28 1 9 pc1 ious port c bit 1 input/output tms/swdi o i/o jtag tms, swd data input/output txd1 input uart0 tx data output 29 20 pc2 ious port c bit 2 input/output tdo/swo output jtag tdo, swo output t8io i/o timer 8 input/output 30 - pc3 ious port c bit 3 input/output tdi input jtag tdi input t9io i/o timer 9 input/output 31 - pc4 ious port c bit 4 input/output ntrst input jtag ntrst input t0io input timer 0 input/output 32 - pc5 ious port c bit 5 input/output rxd1 input uart1 rxd input t1io i/o timer 1 input/output 33 - p c6 ious port c bit 6 input/output txd1 output uart1 txd output
z32f064 1 product specification overview ps03440 4 - 0417 preliminary 10 t2io i/o timer 2 input/output 34 21 pc11 ious port c bit 11 input/output boot input boot mode selection input t9io i/o timer 9 input/output 35 22 pc10 ious port c bit 10 inp ut/output nreset input external reset input pull - up t8io i/o timer 8 input/output 36 23 gnd p ground 37 24 vdd p vdd 38 - pc7 ious port c bit 7 input/output scl0 output i 2 c channel 0 scl in/out t3io i/o timer 3 input/output 39 - pc8 ious port c bit 8input/output sda0 output i 2 c channel 0 sda in/out 40 - pc9 ious port c bit 9 input/output clko output system clock output 41 25 pc15 ious port c bit 14 input/output txd0 output uart0 txd output miso0 i/o spi0 master - inp ut/slave - output 42 26 pc14 ious port c bit 14 input/output rxd0 input uart0 rxd input mosi0 i/o spi0 master - output/slave - input 43 27 pc13 ious port c bit 13 input/output xout oa external crystal oscillator output 44 28 pc12 ious port c bi t 12 input/output xin ia external crystal oscillator input 45 29 pd0 ious port d bit 0 input/output ss0 i/o spi1 slave select t8io i/o timer 8 input/output 46 30 pd1 ious port d bit 1 input/output sck0 i/o spi0 clock input/output t 9io i/o timer 9 input/output 47 31 pd2 ious port d bit 2 input/output miso0 i/o spi channel 0 master in / slave out scl0 output i 2 c channel 0 scl in/out 48 32 pd3* ious port d bit 3 input/output mosi0 i/o spi channel 0 master out / slave i n sda0 output i 2 c channel 0 sda in/out * notation : i=input, o=output, u=pull - up, d=pull - down, s=schmitt - trigger input type, c=cmos input type , a=analog, p=power (*) selected pin function after reset condition pin order may be changed with revis ion notice .
z32f064 1 product specification overview ps03440 4 - 0417 preliminary 11 memory map address memories mapped 0x0000_0000 flash rom (64k b ) 0x0000_ffff 0x0001_0000 reserved 0x0001_ffff 0x0002_0000 reserved 0x1ffe_ffff 0x1fff_0000 boot rom (2kb) 0x1fff_07ff 0x1fff_0800 reserved 0x1fff_ffff 0x2000_0000 sram (8kb ) 0x2000_1fff 0x2000_2000 reserved 0x2fff_ffff 0x3000_0000 flash rom mirrored (64kb) 0x3000_ffff 0x3001_0000 reserved 0x3001_ffff 0x3002_0000 boot rom (2kb) mirror 0x3002_07ff 0x3003_0000 otp mirror 0x3003_07ff 0x3004_0000 reserved 0x3fff_ffff 0x400 0_0000 peripherals 0x4000_ffff 0x4001_0000 reserved 0x5fff_ffff 0x6000_0000 external ram (not support) 0x9fff_ffff 0xa000_0000 external device(not support) 0xdfff_ffff 0xe000_0000 private peripheral bus: internal 0xe003_ffff 0xe004_0000 private periph eral bus: debug/external 0xe00f_ffff 0xe010_0000 0xffff_ffff vendor specific figure 1 . 5 main memory m ap
z32f064 1 product specification overview ps03440 4 - 0417 preliminary 12 address peripherals mapped 0x4000_0000 scu 0x4000_00ff 0x4000_0100 fmc 0x4000_01ff 0x4000_02 00 wdt 0x4000_02ff 0x4000_0300 reserved 0x4000_03ff 0x4000_0400 dmac 0x4000_04ff 0x4000_0500 reserved 0x4000_05ff 0x4000_0600 reserved 0x4000_0fff 0x4000_1000 pcu 0x4000_1fff 0x4000_2000 gpio 0x4000_2fff 0x4000_3000 timer 0x4000_3fff 0x4000_4000 m pwm0 0x4000_4fff 0x4000_5000 reserved 0x4000_7fff 0x4000_8000 uart0 0x4000_80ff 0x4000_8100 uart1 0x4000_81ff 0x4000_8200 reserved 0x4000_8fff 0x4000_9000 spi0 0x4000_90ff 0x4000_9100 reserved 0x4000_9fff 0x4000_a000 i2c0 0x4000_a0ff 0x4000_a100 reserved 0x4000_afff 0x4000_b000 adc0 0x4000_b0ff 0x4000_b100 adc1 0x4000_b1ff 0x4000_b200 0x4000_ffff reserved figure 1 . 6 peripheral memory map
z32f064 1 product specification overview ps03440 4 - 0417 preliminary 13 address core memory map 0xe000_0000 0xe000_0fff itm 0xe000_1000 0xe000_1fff dwt 0xe000_2000 0xe000_2fff fpb 0xe000_3000 0xe000_dfff reserved 0xe000_e000 0xe000_efff system control 0xe000_f000 0xe003_ffff reserved 0xe004_0000 0xe004_0fff tpiu 0xe004_1000 0xe004_1fff etm 0xe004_2000 0xe00f_efff externa l ppb 0xe00f_f000 0xe00f_ffff rom table figure 1 . 7 cortex - m3 private memory map note: refer to d ocument number ddi337 from arm for more information about the memory maps.
z32f064 1 product specification cpu ps03440 4 - 0417 preliminary 14 2. cpu cortex - m3 core the cpu cor e is supported by the arm cortex - m3 processor which provides a high - performance, low - cost platform . document number ddi337 from arm provides more information about cortex - m3 . interrupt controller table 2 . 1 interrupt vector map priority vector address interrupt source - 16 0x0000_0000 stack pointer - 15 0x0000_0004 reset address - 14 0x0000_0008 nmi handler - 13 0x0000_000c hard fault handler - 12 0x0000_0010 mpu fault handler - 11 0x0000_ 0014 bus fault handler - 10 0x0000_0018 usage fault handler - 9 0x0000_001c reserved - 8 0x0000_0020 reserved - 7 0x0000_0024 reserved - 6 0x0000_0028 reserved - 5 0x0000_002c svcall handler - 4 0x0000_0030 debug monitor handle r - 3 0x0000_0034 reserved - 2 0x0000_0038 pensv handler - 1 0x0000_003c systick handler 0 0x0000_0040 lvd detect 1 0x0000_0044 sysclkfail 2 0x0000_0048 xoscfail 3 0x0000_004c wdt 4 0x0000_0050 reserved 5 0x0000_0054 timer0 6 0x0000_0058 timer1 7 0x0000_005c timer2 8 0x0000_00 60 timer3 9 0x0000_0064 reserved 10 0x0000_0068 reserved 11 0x0000_006c reserved 12 0x0000_0070 reserved 13 0x0000_0074 timer 8 14 0x0000_0078 timer 9 15 0x0000_007c reserved 16 0x0000_0080 gpioa e 17 0x0000_0084 gpioao 18 0x0000_0088 gpiobe
z32f064 1 product specification cpu ps03440 4 - 0417 preliminary 15 19 0x0 000_008c gpiobo 20 0x0000_0090 gpioce 21 0x0000_0094 gpioco 22 0x0000_0098 gpiod e 23 0x0000_009c gpiodo 24 0x0000_00a0 mpwm0 25 0x0000_00a4 mpwm0prot 26 0x0000_00a8 mpwm0ovv 27 0x0000_00ac reserved 28 0x0000_00b0 reserved 29 0x0000_00b4 reserved 30 0x0000_00b8 reserved 31 0x0000_00bc reserved 32 0x0000_00c0 spi0 33 0x0000_00c4 reserved 34 0x0000_00c8 reserved 35 0x0000_00cc reserved 36 0x0000_00d0 i2c0 37 0x0000_00d4 reserved 38 0x0000_00d8 uart0 39 0x0000_00dc uart1 40 0x0000_00e0 rese rved 41 0x0000_00e4 reserved 42 0x0000_00e8 reserved 43 0x0000_00ec adc0 44 0x0000_00f0 adc1 45 0x0000_00f4 reserved 46 0x0000_00f8 reserved 47 0x0000_00fc reserved 48 0x0000_0100 reserved 49 0x0000_0104 reserved 50 0x0000_0108 reserved 51 0x000 0_010c reserved 52 0x0000_0110 reserved 53 0x0000_0114 reserved 54 0x0000_0118 reserved 55 0x0000_011c reserved 56 0x0000_0120 reserved 57 0x0000_0124 reserved 58 0x0000_0128 reserved 59 0x0000_012c reserved 60 0x0000_0130 reserved 61 0x0000_0134 reserved 62 0x0000_0138 reserved 63 0x0000_013c reserved
z32f064 1 product specification boot mode ps03440 4 - 0417 preliminary 16 3. boot mode boot mode pins the z32f064 1 mcu includes a b oot m ode option to program internal f lash memory. to enter boot m ode , set the boot pin to l ow at reset timing. note: the n ormal state of the boot pin is h igh . b oot m ode supports uart boot and spi boot.uart boot uses the uart0 port, and spi boot uses spi0.the pins used for b oot m ode are listed in table 3 . 1 . table 3 . 1 boot m ode p in s block pin name dir description system nreset /pc10 i reset input signal boot /pc11 i 0 to enter boot mode uart 0 rxd0 /pc14 i uart boot receive data txd0 /pc15 o uart boot transmit data spi 0 ss 0/pa12 i spi boot slave select sck0 /pa13 i spi boot clock input mosi0 /pa14 i spi boot data input miso0 /pa15 o spi boot data output
z32f064 1 product specification boot mode ps03440 4 - 0417 preliminary 17 boot mode connections d esign the target board using either of the b oot m ode ports C uart or spi. figure 3 . 1 and figure 3 . 2 display sample boot mode connection s . figure 3 . 1 uart boot connection d iagram figure 3 . 2 spi boot connection d iagram z 3 2f 064 1 nreset boot rxd0 txd0 vdd gnd target_ reset boot_sw host_txd host_rxd 3.3 ~ 5v 10k z 3 2f 064 1 nreset boot ss0 sck0 mosi0 miso0 vdd gnd target_ reset boot_sw host_ss host_sck host_sdout host_sdin 3.3 ~ 5v 10k
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 18 4. system control unit o verv iew the z32f064 1 microcontroller has a n in - built intelligent power control block which manages the system analog blocks and operating modes . internal reset and clock signals are controlled by the scu block to maintain optim al system performance and power di ssipation . figure 4 . 1 scu block diagram c lock system the z32f064 1 mcu has the following two main operating clocks : hclk C clock for the cpu and ahb bus system pclk C c lock for p eri pheral systems figure 4 . 2 and figure 4 . 3 show the chips clock system . table 4 .1 lists the clock source descriptions. scu mode control s cu clock gen sleep wake up vdc/lvd/pll intosc control scu wakeup s o u r ce hclk pclk apb bus interrupt interrupt reset
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 19 figure 4 . 2 c lock s o urce c onfiguration figure 4 . 3 system c lock c onfiguration each of the multiplexers for switch ing the clock source contains a circuit which allows glitch - free switching between clock modes . table 4 . 1 clock s ources clock name frequency description mainosc x tal(4mhz~8mhz) external crystal iosc pll clock 8mhz ~ 80 mhz on chip pll r osc 1mh z internal ring osc the pll can synthesize the pllclk clock up to 80 mhz with the fin reference clock. it also has an interna l pre - divider and post - divider. hclk_free (4/8mhz)
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 20 hclk c lock d omain the hclk clock feeds the clock to the cpu and ahb bus. the cortex - m3 cpu requires two clocks related with the hclk clock : fclk C fclk is a free - running cloc k which runs continuously except during p ower - d own m ode hclk C hclk can be stopped during i dle m ode miscellaneous c lock d omain for cortex - m3 figure 4 . 4 mi s cellaneous c lock c onfiguration ringosc mclk xtal systick clk ringosc mclk xtal mpwm0 c lk ringosc mclk xtal timer clk ri ngosc mclk xtal wdt clk ringosc mclk xtal pa_debounce ringosc mclk xtal pb_debounce ringosc mclk xtal pc_debounce ringosc mclk xtal pd_debounce ringosc mclk xtal adc_clk 0xx 100 110 0xx 100 110 0xx 100 110 0xx 100 110 0xx 100 110 0xx 100 110 0xx 100 110 0xx 100 110 0xx 100 110 1/n systickdiv (mccr1) 1/n wdtdiv (mccr3) wdtcsel 1/n timerdiv (mccr3) timercsel 1/n mpwm0div (mccr2) mpwmcsel 1/n adcdiv (mccr7) adccsel 1/n paddiv (mccr4) padcsel 1/n pb ddiv (mccr4) pbdcsel 1/n pcddiv (mccr5) pcdcsel 1/n pdddiv (mccr5) pddcsel
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 21 pclk c lock d omain p clk is the master clock of all the peripherals. it can be stopped in p ower - d own m ode. each peripheral clock i s generated by the pcer register set . clock configuration after power up, the default system clock is fed by the ringosc (1 mhz) clock. ringosc is enabled by default at power up. the other clock sources are enabled by user controls with the ringosc system clock. the mosc clock can be enabled by the cscr register. before enabling the mosc block, the pin mux configuration should be set for xin, xout f unction. pc12 and pc13 pins are shared with moscs xin and xout function - pccmr and pcccr registers should be correctly configured . after enabling the mosc block, you must wait for more than 1 msec to ensure stable operation of crystal oscillation. the pl l clock can be enabled by the pllcon register. after enabling the pll block, you must wait for the pll lock flag. when the pll output clock is stable; you can select mclk for your system requirement. before changing the system clock, f lash access wait shou ld be set to the maximum value. after the system clock is changed, you will need to set the desired f lash access wait time . an example flow chart outlining the steps to configure the system clock is shown in figure 4 . 5 . figure 4 . 5 . clock configuration flow chart when you speed up the system clock up to maximum operating frequency, you should check the flash wait control configuration. flash read access ti me is one of the limiting factors in performance. the wait control recommendation is provided in table 4 . 2 . p o w e r u p m c l k = = r i n g o s c ( d e f a u l t s e t ) s e t f l a s h w a i t c o n t r o l i n f m . c f g . w a i t = = m a x i m u m w a i t s e t m o s c p c c m r [ 2 7 : 2 4 ] x i n , x o u t p c c c r [ 2 7 : 2 4 ] a n a l o g c s c r . e o s c c o n [ 1 ] = 1 c h e c k e o s c s t s b i t i n c m r w a i t 5 m s e c f o r m o s c c r y s t a l o s c i l l a t i o n s t a b i l i z i n g c h a n g e m c l k f r o m r i n g o s c t o m o s c i n s c c r ( m c l k = = m o s c ) s e t p l l c o n c h e c k p l l l o c k b i t i n p l l c o n c h a n g e m c l k f r o m m o s c t o p l l i n s c c r ( m c l k = = p l l ) s e t f l a s h w a i t c o n t r o l i n f m . c f g . w a i t e n d y n y n
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 22 table 4 . 2 . flash wait control recommendation fm.cfg.wait flash access wa it available max system clock frequency 000 0 clock wait ~16mhz 001 1 clock wait ~32mhz 010 2 clock wait ~48mhz 011 3 clock wait ~48mhz reset the z32f064 1 mcu has two system resets: ? cold reset by por, which is effective during power up or down sequenc e, and ? warm reset, which is generated by several reset sources. the reset event causes the chip to return to initial state. the cold reset has only one reset source , por. the warm reset has the following reset sources : ? nreset pin ? wdt reset ? lvd reset ? mclk fail reset ? mosc fail reset ? s/w reset ? cpu request reset cold reset cold reset is an important feature of the chip when power is up. this characteristic globally affects the system boot. internal vdc is enabled when vdd power is turned on. the internal vdd level slope is followed by the external vdd power slope. the internal por trigger level is 1.4 v of internal vdc voltage out level. at this time, boot operation is started. the ringosc clock is enabled and counts to 4 msec for internal vdc level stabilizi ng. during this time, the external vdd voltage level should be greater than the initial lvd level (2.3 v). after counting 4 msec, the cpu reset is released and the operation is started. figure 4.6 shows the power up sequence and internal reset waveform .
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 23 figure 4 . 6 . power - up por s equence the rssr register shows the por reset status. the last reset comes from por; rssr.porst is set to 1. after power up, this bit is always 1. if an abnormal internal voltage drop occurs during normal operation, the system will be reset a nd this bit is also set to 1. when cold reset is applied, the chi p returns to its initial state. warm reset the warm reset event has several reset sources. som e parts of the chip return to initial state when a warm reset condition occurs. the warm reset source is controlled by the rser register and the status appears in the rssr register. the reset for each peripheral block is controlled by the prer register. th e reset can be masked independently.
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 24 figure 4 . 7 . reset configuration
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 25 o peration mode the init mode is the initial state of the chip when reset is asserted. the run mode is for m aximum performance of the cpu with a high - speed clock system. the sleep mode can be used as the low - power consumption mode. low - power consumption is achieved by halting the process or core and unused peripherals. figure 4 . 8 show s the operating mode transition diagram. figure 4 . 8 . operating mode run mode in run mode, the cpu core and the peripheral hardware is operated by using the high - speed clock. after reset, followed by the ini t state, the chip enters run mode. sleep mode in sleep mode, only the cpu is stopped. each peripheral function can be enabled by the function enable and clock enable bit in the per and pcer register. wfi sleepdeep=0 mcu initialization power - on reset run wake - up event init reset event sleep reset event
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 26 p in d escription table 4 . 3 scu and pll p ins pin name t ype d escription nreset i external reset input xin / xout osc external crystal oscillator stbyo o stand - by output signal clko o clock output monitoring signal r egisters the b ase a ddress of the system contro l unit is 0x4000_0000 and the register map is described in table 4 . 4 . table 4 . 4 scu register map n ame o ffset t ype d escription r eset v alue c idr 0x 0000 r chip id register ac33_ 4064 s m r 0x 0004 rw system mode register 0000 _0000 s r cr 0x 0008 rw system reset control register 0000 _0000 w u er 0x 0010 rw wake up source enable register 0000 _ 00 00 w u sr 0x 0014 rw wake up source status register 0000 _ 0000 rser 0x 0018 rw reset source enable registe r 0000 _ 00 49 rssr 0x 001c rw reset source status register 0000 _ 00 8 0 * p r e r 1 0x 0020 rw peripheral reset enable register 1 0 3 0 f _0 f 3 f* p re r 2 0x 002 4 rw peripheral reset enable register 2 00 31 _0 311 * per 1 0x 002 8 rw peripheral enable register 1 0000_000f * per2 0x002c rw peripheral enable register 2 00 00 _0 101 * pcer1 0x0030 rw peripheral clock enable register 1 0 000 _ 000f * pc er2 0x 00 34 rw peripheral clock enable register 2 00 00 _0 101 * cscr 0x0040 rw clock source control register 0000_0020 sccr 0x 00 44 rw system c lock c ontrol register 0000_0000 cmr 0x 00 48 rw clock monitoring register 0000 _00 90 nmi r 0x004c rw nmi control register 0000 _0000 cor 0x 00 50 rw clock output control register 0000 _000f pllcon 0x 00 6 0 rw pll control register 0000 _ 0 000 vdccon 0x 00 6 4 rw vdc control register 0 000 _000f lv dcon 0x 00 6 8 rw lv d control register 0 000_0001 eoscr 0x0080 rw external o scillator control register 0000_0 3 00 emodr 0x 00 84 rw external mode pin read register 0000_000 x dbclk1 0x009c rw debounce clock control register 1 0001_ 0001 dbclk2 0x00a0 rw debounce clock control register 2 0001_0001 mccr1 0x0090 rw misc clock control register 1 0000 _ 000 0 mccr2 0x0094 rw misc clock control register 2 000 0_ 000 0 mccr3 0x0098 rw m isc clock control register 3 0000_0001 mccr 4 0x00a8 rw m isc clock control register 4 0001_0000
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 27 c idr chip id register the chip id register shows chip identification information. this register is a 32 - bit read - only register. cidr= 0x4000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 chipid 0xac33_4064 ro 31 0 chipid device id 0xac33_4064 cidr=0x4000_000c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 chipid2 0x0000_0000 ro 31 0 chipid2 revision id 0x0000_0000 s mr system mode register the c urrent operating mode is shown in this scu mode register .t he operat ing mode can be changed by writing a new mode in this register. the previous operating mode will be saved in this register after a reset event . the system mode register is a 16 - bit register. smr= 0x4000_000 4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 prevmode 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 r 5 4 prevmode previous operating mode before current reset event. 00 previous operating mode was run mode 01 previous operating mode was sleep mode 10 previous operating mode was powerdown mode 11 previous operating mode was init mode
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 28 s r c r s ystem reset control register the system r eset c ontrol register allows the software to initate a reset. this register also provides the polarity for the stbyop pin. scr= 0x4000_000 8 7 6 5 4 3 2 1 0 swrst 0 0 0 0 0 0 0 0 w 1 swrst internal soft reset activation bit 0 normal operation 1 internal soft reset is applied and auto cleared
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 29 w u er wakeup source enable register enable the wakeup source when the chip is in power - down m ode. t he source of chip wakeup should be enabled in each bit field for wakeup sources that will be used . if the source is used as a wakeup source, the corresponding bit should be writ t e n as 1 . if the source is not used as a wakeup source, the bit should be wri t te n as 0 . the wakeup source enable register is a 16 - bit register. wuer= - 0x4000_00 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gpiodwue gpiocwue gpiobwue gpioawue wdtwue lv dwue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rw rw rw rw rw rw 11 gpiodwue enable wakeup source of gpiod port pin change event 0 not used for wakeup source 1 enable the wakeup event generation 10 gpiocwue ena ble wakeup sour ce of gpioc port pin change even t 0 not used for wakeup source 1 enable the wakeup event generation 9 gpiobwue enable wakeup source of gpiob port pin change event 0 not used for wakeup source 1 enable the wakeup event generatio n 8 gpioawue enable wakeup source of gpioa port pin change event 0 not used for wakeup source 1 enable the wakeup event generation 1 wdtwue enable wakeup source of watchdog timer event 0 not used for wakeup source 1 enable the wakeup event generation 0 lvdwue enable wakeup source of lvd event 0 not used for wakeup source 1 enable the wakeup event generation
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 30 w u sr wakeup source status register when the system is w oken up by any wakeup source, the wakeup source is identified by rea ding the wakeup source status r egister. when the bit is set to 1 , the related wakeup source issues the wake - up signal to the scu . the bit is cleared when the event source is cleared by the software . these bits show the interrupt flag in each peripheral. e xamples: a gpio wakeup status is cleared by clearing the interrupt flag in the pcn.isr register of the pcu block. a wdtwu interrupt is cleared by clearing the overflow interrupt flag in the wdt block. the lvd flag is cleared when the low voltage condition is resolved. wusr= 0x4000_0014 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gpiodwu gpiocwu gpiobwu gpioawu wdtwu lv dwu 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r r r r r r 11 gpiodwu status of wakeup source of gpiod port pin change event 0 n o wakeup event 1 wakeup event was generated 10 gpiocwu status of wakeup source of gpioc port pin change event 0 no wakeup event 1 wakeup event was generated 9 gpiobwu status of wakeup source of gpiob port pin change event 0 no wakeup event 1 wakeup event was generated 8 gpioawu status of wakeup source of gpioa port pin change event 0 no wakeup event 1 wakeup event was generated 1 wdtwu status of wakeup source of watchdog timer event 0 no wakeup event 1 wakeup event was g enerated 0 lvdwu status of wakeup source of lvd event 0 no wakeup event 1 wakeup event was generated
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 31 rser reset source enable register the reset source to the cpu is selected by the reset source enable r egister. when 1 is written in the bit fi eld of each reset source, the reset source event is transferred to the reset generator. when 0 is written in the bit field of each reset source, the reset source event is masked and does not generate a reset event. rser= 0x4000_0018 7 6 5 4 3 2 1 0 pinr st core rst swrst wdtrst mckfrst xfrst lvdrst 0 1 0 0 1 0 0 1 rw rw rw rw rw rw rw 6 pinrst external pin reset enable bit 0 reset from this event is masked 1 reset from this event is enabled 5 cpurst cpu request reset enable bit 0 reset fr om this event is masked 1 reset from this event is enabled 4 swrst software reset enable bit 0 reset from this event is masked 1 reset from this event is enabled 3 wdtrst watchdog timer reset enable bit 0 reset from this event is masked 1 reset from this event is enabled 2 mckfrst mclk clock fail reset enable bit 0 reset from this event is masked 1 reset from this event is enabled 1 xfrst external osc clock fail reset enable bit 0 reset from this event is masked 1 reset from this event is enabled 0 lvdrst lvd reset enable bit 0 reset from this event is masked 1 reset from this event is enabled
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 32 rssr reset source status register the r eset source status register displays t he reset source information when a reset event occurs . 1 indicates that a reset event exist s and 0 indicates that a reset event does not exist for a given reset source.when a reset source is found , write 1 to the corresponding bit to clear the reset status. this register is an 8 - bit regi ster . rssr= 0x4000_001 c 7 6 5 4 3 2 1 0 porst pinrst cpu rst swrst wdtrst mckfrst xfrst lvdrst 1 0 0 0 0 0 0 0 rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1 7 porst power on reset status bit 0 read : reset from this event was not exist write : no effect 1 read :reset from this event was occurred write : clear the status 6 pinrst external pin reset status bit 0 read : reset from this event was not exist write : no effect 1 read :reset from this event was occurred write : clear the status 5 cpurst cpu req uest reset status bit 0 read : reset from this event was not exist write : no effect 1 read :reset from this event was occurred write : clear the status 4 swrst software reset status bit 0 read : reset from this event was not exist write : no eff ect 1 read :reset from this event was occurred write : clear the status 3 wdtrst watchdog timer reset status bit 0 read : reset from this event was not exist write : no effect 1 read :reset from this event was occurred write : clear the status 2 mclkfrst mclk fail reset status bit 0 read : reset from this event was not exist write : no effect 1 read :reset from this event was occurred write : clear the status 1 xfrst clock fail reset status bit 0 read : reset from this event was not exi st write : no effect 1 read :reset from this event was occurred write : clear the status 0 lvdrst lvd reset status bit 0 read : reset from this event was not exist write : no effect 1 read :reset from this event was occurred write : clear the sta tus
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 33 pr e r 1 peripheral reset enable register 1 the reset of each peripheral by e vent r eset can be masked by this user setting. the prer 1 /prer 2 register control s enable ment of the event reset. if the corresponding bit is 1 , the peripheral correspon ding to this bit accepts the reset event. o therwise, the peripheral is protected from the reset event and maintain s its current operation. prer1= 0x4000_0020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 timer9 time r8 timer3 timer2 timer1 timer0 gpiod gpioc gpiob gpioa dma pcu wdt fmc scu 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 2 5 timer 9 timer 9 reset mask 2 4 timer 8 t imer 8 reset mask 19 timer3 timer3 reset mask 18 timer2 timer2 reset mask 17 timer1 timer1 reset mask 16 timer0 timer0 reset mask 11 gpiod gpioe reset mask 10 gpioc gpioe reset mask 9 gpiob gpioe reset mask 8 gpioa gpioa reset mask 4 dma dma reset mask 3 pcu port control unit reset mask 2 wdt watchdog timer reset mask 1 fmc flash memory controller reset mask 0 scu system control unit reset mask
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 34 prer2 peripheral reset enable register 2 the reset of each peripheral by e vent r eset can be masked by this user setting. the prer1/prer2 register control s enable ment of the event reset. if the corresponding bit is 1 , the peripheral correspon ding to this bit accepts the reset event. o therwise, the peripheral is protected from the reset event and maintai ns its current operation. prer2=0x4000_0024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 adc1 adc0 mwpm0 uart1 uart0 i2c0 spi0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 rw rw rw rw rw rw rw 21 adc1 adc1 reset enable 20 adc0 adc0 reset enable 16 mpwm0 mpwm0 reset enable 9 uart1 uart1 reset enable 8 uart0 uart0 reset enable 4 i2c0 i 2 c0 reset enable 0 spi0 spi0 reset enable
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 35 per1 peri pheral enable register 1 prior to using a peripheral unit, it requires to be activated by writing 1 to the correspond ing bit in the per 1 /per 2 r egister. until activation, the peripheral stay s in r eset state. to disable the peripheral unit, write 0 to the co rrespond ing bit in the per0/ per 1 register, after which the peripheral enter s the r eset state. per1= 0x4000_002 8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 timer9 timer8 timer3 timer2 timer1 timer0 g piod gpioc gpiob gpioa dma 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 rw rw rw rw rw rw rw rw rw rw rw r r r r 2 5 timer 9 timer 9 function enable 2 4 timer 8 timer 8 function enable 19 timer3 timer3 function en able 18 timer2 timer2 function enable 17 timer1 timer1 function enable 16 timer0 timer0 function enable 11 gpiod gpio d function enable 10 gpioc gpio c function enable 9 gpiob gpio b function enable 8 gpioa gpioa function enable 4 dma dma function ena ble 3 reserved 2 1 0
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 36 per2 peripheral enable register 2 prior to using a peripheral unit, it requires to be activated by writing 1 to the correspond ing bit in the per1/per2 r egister. until activation, the peripheral stay s in r eset state. to di sable the peripheral unit, write 0 to the correspond ing bit in the per0/per1 register, after which the peripheral enter s the r eset state. per2=0x4000_002c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 adc 1 adc0 mwpm0 uart1 uart0 i2c0 spi0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 rw rw rw rw rw rw rw 21 adc1 adc1 function enable 20 adc0 adc0 function enable 16 mpwm0 mpwm0 function enable 9 uart1 uart1 function enable 8 uart0 uart0 function enable 4 i2c0 i 2 c0 function enable 0 spi0 spi0 function enable
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 37 pcer 1 per ipheral clock enable register 1 prior to using a peripheral unit, its clock should be activated by writing 1 to the correspon d ing bit in the p c er 1 / pcer 2 register. t he peripheral w ill not operate correctly until its clock is enabled . to stop the clock of the peripheral unit, write 0 to the correspond ing bit in the p c er 1 / pcer 2 register . pcer1= 0x4000_00 3 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 timer9 timer8 timer3 timer2 timer1 timer0 gpiod gpioc gpiob gpioa dma 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 rw rw rw rw rw rw rw r w rw rw rw r r r r 25 timer9 timer9 clock enable 24 timer8 timer8 clock enable 19 timer3 timer3 clock enable 18 timer2 timer2 clock enable 17 timer1 timer1 clock enable 16 timer0 timer0 clock enable 11 gpiod gpio d clock enable 10 gpioc gpio c cl ock enable 9 gpiob gpio b clock enable 8 gpioa gpioa clock enable 4 dma dma clock enable 3 reserved 2 1 0
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 38 pcer2 peripheral clock enable register 2 prior to using a peripheral unit, its clock should be activated by writing 1 to the correspon ding bit in the pcer1/pcer2 register. t he peripheral w ill not operate correctly until its clock is enabled . to stop the clock of the peripheral unit, write 0 to the correspond ing bit in the pcer1/pcer2 register . pcer2=0x4000_0034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 adc1 adc0 mwpm0 uart1 uart0 i2c0 spi0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 rw rw rw rw rw rw rw 21 adc1 adc1 c lock enable 20 adc0 adc0 clock enable 16 mpwm0 mpwm0clock enable 9 uart1 uart1 clock enable 8 uart0 uart0 clock enable 4 i2c0 i 2 c0 clock enable 0 spi0 spi0 clock enable
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 39 c scr clock source control register the z32f064 1 mcu has multiple clock sources to generate internal operating clocks. e ach clock source can be controlled by the c lock source control r egister. this register is an 8 - bit register. cscr= 0x4000_00 40 7 6 5 4 3 2 1 0 - ring osccon - e osccon 00 10 00 00 r r w r r w 5 4 ring osccon internal ring oscillator control 0 x stop internal sub oscillator 10 enable internal sub oscillator 11 enable internal sub oscillator divide by 2 1 0 e osc c on e xternal crystal oscillator control 0 x stop external ctystal oscillator 10 enable external ctystal oscillator 11 enable external ctystal divide by 2
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 40 sccr system clock control register the z32f064 1 mcu has multiple clock sources to generate internal oper ating clocks. each clock source can be controlled by the system clock control r egister . the mosc must be running and stable before setting the finsel bit. sccr= 0x4000_00 44 7 6 5 4 3 2 1 0 - finsel mclksel 0000 0 00 r rw rw 2 finsel pll input source fin select register 0 iosc clock is used as fin clock 1 mosc clock is used as fi n clock 1 0 mclksel system clock select register 0 x internal sub oscillator 10 pll bypassed clock 11 pll output clock note: when chang ing finsel, both internal osc and external osc should be alive to prevent the chip from mal function ing.
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 41 cm r clock monit oring register to monitor the i nternal clock and external oscillator, the mclkmnt/eoscmnt bits must be set before the mclk and eosc bits are valid. the clock monitoring register is a 16 - bit register. note: the eosc bit only checks for the eosc oscillation, not its stability. when the system detects an mclkfail interrupt, the mclkrec bit determines if the system dies or will auto - recover using the rosc. the system usually auto - recovers so that it can continue running. cmr= 0x4000_0048 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mclkrec mclkmnt mclkie mclkfail mclksts eosc mnt eosc ie eoscf ail eosc sts 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 r rw rw rc1 rc1 rw rw rc1 rc1 15 mclkrec mclk fail auto recovery 0 mclk is changed to ringosc by defa ult when mclkfail issued 1 mclk auto recovery is disabled 7 mclkmnt mclk monitoring enable 0 mclk monitoring disabled 1 mclk monitoring enabled 6 mclkie mclk fail interrupt enable 0 mclk fail interrupt disabled 1 mclk fail interrupt enabl ed 5 mclkfail mclk fail interrupt 0 mclk fail interrupt not occurred 1 read : mclk fail interrupt is pending write : clear pending interrupt 4 mclksts mclk clock status 0 no clock is present on mclk 1 clock is present on mclk 3 eoscmnt exte rnal oscillator monitoring enable 0 external oscillator monitoring disabled 1 external oscillator monitoring enabled 2 eoscie external oscillator fail interrupt enable 0 external oscillator fail interrupt disabled 1 external oscillator fail i nterrupt enabled 1 eoscfail external oscillator fail interrupt 0 external oscillator fail interrupt not occurred 1 read : external oscillator fail interrupt is pending write : clear pending interrupt 0 eoscsts external oscillator status 0 not o scillate 1 external oscillator is working normally the c lock m onitoring function cannot cover all malfunction cases and is only used for reference. figure 4 . 9 shows the operational diagram for clock monitoring function.
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 42 figure 4 . 9 . clock monitoring function diagram
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 43 nmi r n on - maskable interrupt control register th e n on - m askable i nterrupt control r egister can be set with software. there are five kinds of interrupt sources from mpwm, wdt , and scu. write access key 0xa32c to nmr[31:16] is required before writing to this register. nmir=0x4000_004c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 accesscode protsts ovpsts wdtsts mclkfailsts lvdsts proten ovpen wdten mclkfailen lvden - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wo r r r r r rw rw rw rw rw 31 16 accesscode this field enables writing access to this register. writing 0xa32c is to enable writing. 12 p rotsts protection condition status bit. this bit cant invoke nmi interrupt without enable bit this bit cant invoke nmi interrupt without enable bit this bit cant invoke nmi interrupt without enable bit this bit cant invoke nmi interrupt with this bit cant invoke nmi interrupt without enable bit
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 44 cor clock output register the z32f064 1 mcu can drive the clock from internal mclk cloc k with a dedicated post divider. the clock output register is an 8 - bit register. cor= 0x4000_ 0050 7 6 5 4 3 2 1 0 - clkoen clkodiv 000 0 1111 r rw rw 4 clkoen clock output enable 0 clko is disabled and stay l output ?? ?? = ???? ? ? ( ??????? + ? ) ( ??????? > ? )
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 45 pllcon pll control register integrated pll can synthesize the high speed clock for extremely high performance of the cpu from either the internal oscillator (iosc) or the external oscillato r (mosc) . the p ll control register provides the configuration for the pll system. by default, the pll system is in reset mode and disabled. you must negate the reset and enable the pll to operate (bits 14 and 15 must be set). the bypass bit must be set to output the pll clock. the active clock is defined in sccr bit 2 (fin). to calculate the pll output: pll out = ((active clock / prediv) * fbctrl) / postdiv for example: using mosc (assuming it is running at 8 mhz and selected): prediv set to 1 (f in / 2) fbctrl set to 0x04 (m=12) postdiv set to 0x00 (n=1) ((8 mhz / 2) * 12) = 48 mhz pllcon= 0x4000_00 6 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pllrstb pllen bypass locksts prediv fbctrl postdiv 0 0 0 0 0 0 0 0 0000 0000 rw rw rw r rw rw rw 15 pllrstb pll reset 0 pll r eset is asserted 1 pll reset is negated 14 pllen pll enable 0 pll is disabled 1 pll is enabled 1 3 bypass fin bypass 0 fout is bypassed as fin 1 fout is pll output 12 lock lock status 0 pl l is not locked 1 pll is locked 8 prediv fin predivider 0 fin divided by 1 1 fin divided by 2 7 4 fbctrl feedback control 0000 m = 4 1000 m = 20 0001 m = 6 1001 m = 24 0010 m = 8 1010 m = 26 0011 m = 10 1011 m = 34 0100 m = 12 110 0 not available 0101 m = 14 1101 0110 m = 16 1110 0111 m = 18 1111 3 0 postdiv post divider control 000 n = 1 001 n = 2 010 n = 3
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 46 011 n = 4 100 n = 6 101 n = 8 110 n = 3 111 n =16 vdccon vdc control register t he o n chip vdc control register , vdctrim , is used for the trim value of vdc output. to modify the vdctrim bit, 1 should be written to vdcte simultaneously . the vdcwdly value can be written by writing 1 to the vdcde bit simultaneously. vdccon=0x4000_0064 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserve reserved vdcte vdctrim vdcde vdcwdly 0 0 0 0 0 00 0 0 0 0 0000 0 0 0 0 0 0 0 0 0x 7 f w rw w rw w rw 23 vdcte vdctrim value write e nable. write only with vdctrim value. 0 vdctrim field is not updated by writing 1 vdctrim filed can be updated by writing 19 16 vdctrim vdc output voltage trim value 8 vdcde vdcwdly value write enable. write only with vdcwd ly value 0 fout is pl l output 1 fout is bypassed as fin 7 0 vdcwdly vdc warm - up delay count value. when scu is waked up from powerdown mode, the w arm - up delay is inserted for vdc output being stabilize d. the amount of delay can be defined with this register value 7f : 2ms ec
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 47 lvd con lvd control register the lvd control register is an o n chip b rown - out detector control register. this register is a 32 - bit register. lvd con= 0x4000_00 6 8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lvd te lvd trim selen lvd sel lvd lvl lvd en 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 rw rw r o rw ro rw 2 3 lvd te lvd trim value write enable. write only with lvd trim value. 0 lvd trim fiel d is not updated by writing 1 lvd trim filed can be updated by writing 17 16 lvd trim lvd voltage level trim value it can writable when trim enable mode in fmc 15 selen lvd level sel value write enable. write only. 0 sel field is not updated by writi ng 1 sel filed can be updated by writing 9 8 lvd sel lvd detect level select 00 lvd detect level is 1.8v - 50mv 01 lvd detect level is 2.2v C C
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 48 eosc r external o scillator control register the e xternal main crystal oscillator has two characte ristics. for noise immunity, the nmos amp type is recommended and for low power , the inv amp type is recommended. this register is a 16 - bit register. eoscr = 0x4000_0080 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 iselen isel 0 0 0 0 0 0 11 0 0 0 0 0 0 0 0 w rw 15 isel en write enable of bit field isel . 0 write access of isel field is masked 1 write access of isel field is accepted 9 8 isel select current. 00 minimum current driving option 01 low current driving option 10 high current driving option 11 maximum current driving option emodr external mode status register external mode status register shows the external mode pin status while booting. this register is an 8 - bit register. emodr= 0x4000_0084 7 6 5 4 3 2 1 0 boot 0 x0 0 0 - r r r r 0 boot boot pin level 0 boot(pc11) pin is low 1 boot(pc11) pin is high
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 49 dbclk1 debounce clock control register 1 the debounce clock control register 1 controls the debounce timing configuration for port a and por t b. dbclk1 =0x4000_009c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pbdcsel pbddiv padcsel paddiv 0 0 0 0 0 000 0x01 0 0 0 0 0 000 0x01 rw rw rw rw 26 24 pbdcsel debounce clock for port b source select bit 0xx ring osc 1mhz 100 mclk (bus clock) 101 reserved 110 external main osc (xtal) 111 reserved 23 16 pbddiv port b debounce clock n divider 10 8 padcsel debounce clock for port a source select bit 0xx ring osc 1 mhz 100 mclk (bus clock) 101 reserved 110 external main osc (xtal) 111 reserved 7 0 paddiv port a debounce clock n divider
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 50 dbclk2 debounce clock control register 2 the debounce clock control register 2 controls the debounce timing configura tion for port c and port d. dbclk2 =0x4000_00a0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pddcsel pdddiv pcdcsel pcddiv 0 0 0 0 0 000 0x01 0 0 0 0 0 000 0x01 rw rw rw rw 26 24 pddcsel de bounce clock for port d source select bit 0xx ring osc 1mhz 100 mclk (bus clock) 101 reserved 110 external main osc (xtal) 111 reserved 23 16 pdddiv port d debounce clock n divider 10 8 pcdcsel debounce clock for port c source sele ct bit 0xx ring osc 1mhz 100 mclk (bus clock) 101 reserved 110 external main osc (xtal) 111 reserved 7 0 pcddiv port c debounce clock n divider mccr 1 miscellaneous clock control register 1 the miscellaneous clock control register 1 controls the configuration for the system tick clocks. mccr1= 0x4000_0090 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 stcsel systickdiv 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0x01 rw rw 10 8 s t csel systic clock source select bit 0xx ring osc 1mhz 100 mclk (bus clock) 101 reserved 110 external main osc (xtal) 111 reserved 7 0 st div systic clock n divider
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 51 mccr 2 miscellaneous clock cont rol register 2 the miscellaneous clock control register 2 controls the optional configuration of mpwm0 clocks. mccr2= 0x4000_0094 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pwm0csel pwm0div 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0x0 0 rw rw 10 8 pwm0 c sel pwm0 clock source select bit 0xx ring osc 1mhz 100 mclk (bus clock) 101 reserved 110 external main osc (xtal) 111 reserved 7 0 pwm0div pwm0 clock n divider mccr 3 miscellaneous clock control register 3 the miscellaneous clock control register 3 controls the configuration for the timer ext0 and wdt clocks. mccr3= 0x4000_009 8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t ext0 csel text0div wdtcsel wdtdiv 0 0 0 0 0 000 0x01 0 0 0 0 0 000 0x01 rw rw rw rw 26 24 t ext0 csel t imer ext0 clock source select bit 0xx ring osc 1mhz 100 mclk (bus clock) 101 reserved 110 extern al main osc (xtal) 111 reserved 23 16 tex t 0 div timer ext0 clock n divider 10 8 wdt csel wdt clock source select bit 0xx ring osc 1mhz 100 mclk (bus clock) 101 reserved 110 external main osc (xtal) 111 reserved 7 0 wdt div wdt clock n di vider
z32f064 1 product specification system control unit ps03440 4 - 0417 preliminary 52 mccr 4 miscellaneous clock control register 4 the miscellaneous clock control register 4 controls the clock setting for the adc peripheral. mccr7= 0x4000_00 a 8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 adccsel adccdiv 0 0 0 0 0 000 0x01 rw rw 26 24 adccsel adc clock source select bit 0xx ring osc 1mhz 100 mclk (bus clock) 101 reserved 110 external main osc (xtal) 111 reser ved 23 16 adccdiv adc clock n divider
z32f064 1 product specification port control unit ps03440 4 - 0417 preliminary 53 5. p ort c ontrol u nit o verview the port control unit (pcu ) controls the external i/o configuration to: ? set the multiplex state of each pin (for alternative functions) ? set external signal type (analog / push - pull ou tput /open drain output /input) ? set enable/monitor/trigger type for interrupt s for each pin ? set internal pull - up register control for each pin ? set debounce for each pin note: you must enable both the port periphreal and the port periphreal clock in per1/p cer1/ to use the pins of the port. figure 5 . 1 block diagram pa/pb/pc pd/pe/pf port cont rol function mux interrupt control ports function i/os apb bus nvic
z32f064 1 product specification port control unit ps03440 4 - 0417 preliminary 54 figure 5 . 2 i /o port block diagram (adc and ext ernal oscillator pins ) figure 5 . 3 i/o port block diagram ( general i/o pins ) 0 1 00 01 10 11 vddio vddio debounce logic function input debounce enab le debounce count open - drain enable input mode pull - up enable port mux gpio output function 1 output function 1 output function 3 output analog disable * pin vddio pin 0 1 00 01 10 11 vddio vddio debounce logic function input debounce enable debounce count open - drain enable input mode pull - up enable port mux gpio ou tput function 1 output function 1 output function 3 output analog disable analog input (an0~an15, xtali,xtalo, sxin,sxout) vddio
z32f064 1 product specification port co ntrol unit ps03440 4 - 0417 preliminary 55 pin multiplexing gpio pins have alternative function pins. table 5 . 1 table 5 . 1 gpio alternative function shows pin multiplexing information . table 5 . 1 gpio alternative function p ort p in function 00 01 10 11 pa 0 pa0 * an0 1 pa1 * an1 2 pa 2 * wdto an2 3 pa3 * an3 4 pa4 * ss1 an4 5 pa5 * ss2 an5 6 pa6 * t0io t2 i o an6 7 pa7 * t1io t3 i o an 7 8 pa8 * t2io t0io an8 9 pa9 * t3io t1io an9 10 pa10 * ss3 an10 11 pa11 * 12 pa12 * t0io 13 pa13 * t1io 14 pa14 * t2io 15 pa15 * t3io pb 0 pb0 * m p0 u h 1 pb1 * m p0 u l 2 pb2 * m p0 v h 3 pb3 * m p0 v l 4 pb4 * m p0 w h 5 pb5 * m p0 w l 6 pb6 * prtin 0 t0io 7 pb7 * ovin 0 t1io 8 9 10 11 12 13 14 15 (*) indicates default pin setti ng (2) indicates secondary port
z32f064 1 product specification port control unit ps03440 4 - 0417 preliminary 56 table 5 . 2 gpio alternative f unction p ort p in f unction 00 01 10 11 pc 0 pc0 tck/swclk * rxd1 1 pc1 tms/swdio * txd1 2 pc2 tdo/swo * t8io 3 pc3 tdi * t9io 4 pc4 ntrs t * t0io 5 pc5 * rxd1 t1io 6 pc6 * txd1 t2io 7 pc7 * scl0 t3io 8 pc8 * sda0 9 pc9 * clko 10 pc10 nreset * t8 i o 11 pc11 /boot * t9io 12 pc12 * xin 13 pc13 * xout 14 pc14 * rxd0 m o s i 0 (2) 15 pc15 * txd0 m i s o 0 (2) pd 0 pd0 * ss 0 t8io 1 pd1 * sck 0 t9io 2 pd2 * mosi 0 scl0 3 pd3 * miso 0 sda0 4 5 6 7 8 9 10 11 12 13 14 15 (*) indicates default pin setting. (2) indicates secondary port
z32f064 1 product specification port control unit ps03440 4 - 0417 preliminary 57 r egisters the b ase addres s of the pcu block is 0x4000_1000 . table 5 . 3 base a ddress of p ort port name address p c a 0x4000_1000 p c b 0x4000_1100 p c c 0x4000_1200 p c d 0x4000_1300 table 5 . 4 p cu register m ap n ame offset type description p c n . mr 0x -- 00 rw port n pin mux select register p c n . cr 0x -- 04 rw port n pin control register p c n . pcr 0x -- 08 rw port n internal pull - up control register p c n . der 0x -- 0c rw port n debounce control register p c n . ier 0x -- 10 rw port n interrupt enable register p c n . isr 0x -- 14 rw port n interrupt status register p c n . icr 0x -- 18 rw port n interrupt control register 0x -- 1c reserved porten 0x1ff0 rw port access enable
z32f064 1 product specification port control unit ps03440 4 - 0417 preliminary 58 p c a . mr port a pin mux register this register is the pa p ort m ode select register , and must be set up correctly before us ing the port to ensure that the port functions as designed. p c a . mr=0x4000_1000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pa1 5 pa14 pa13 pa12 pa11 pa10 pa9 pa8 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw p ort selection bit 00 01 10 11 pa 0 pa0 * an0 pa 1 pa1 * an1 pa 2 pa2 * wdto an2 pa 3 pa3 * an3 pa 4 pa4 * ss1 an4 pa 5 pa5 * ss2 an5 pa 6 pa6 * t0io t2 i o an6 pa 7 pa7 * t1io t3 i o an7 pa 8 pa8 * t2io t0io an8 pa 9 pa9 * t3io t1io an9 pa 10 pa10 * ss3 an10 pa 11 pa11 * pa 12 pa12 * t0io pa 13 pa13 * t1io pa 14 pa14 * t2io pa 15 pa15 * t3io
z32f064 1 product specification port control unit ps03440 4 - 0417 preliminary 59 p c b . mr port b pin mux register this register is the p b p ort m ode select register , and must be set up correctly before us ing the port to ensure that the port functions as designed. p cb . mr=0x4000_1100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pb15 pb14 pb13 pb12 pb11 pb10 pb9 pb8 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw p ort selection bit 00 01 10 11 p b0 pb0 * mp0u h p b1 pb1 * mp0ul p b2 pb2 * mp0vh p b3 pb3 * mp0vl p b4 pb4 * mp0wh p b5 pb5 * mp0wl p b6 pb6 * prtin0 t0io p b7 pb7 * ovin0 t1io
z32f064 1 product specification port control unit ps03440 4 - 0417 preliminary 60 p c c . mr port c pin mux register this register is the p c p ort m ode select register , and must be set up correctly be fore us ing the port to ensure that the port functions as designed. p cc . mr=0x4000_1200 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 00 00 00 0 0 0 1 0 1 00 00 00 00 00 0 1 0 1 0 1 0 1 0 1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw p ort selection bit 00 01 10 11 pc 0 pc0 tck/swclk* rxd1 pc 1 pc1 tms/swdio* txd1 pc 2 pc2 tdo/swo* t8io pc 3 pc3 tdi* t9io pc 4 pc4 ntrst* t0io pc 5 pc5 * rxd1 t 1io pc 6 pc6 * txd1 t2io pc 7 pc7 * scl0 t3io pc 8 pc8 * sda0 pc 9 pc9 * clko pc 10 pc10 nreset * t8 i o pc 11 pc11 /boot * t9io pc 12 pc12 * xin pc 13 pc13 * xout pc 14 pc14 * rxd0 mo s i 0 (2) pc 15 pc15 * txd0 m i s o 0 (2)
z32f064 1 product specification port control unit ps03440 4 - 0417 preliminary 61 p c d . mr port d pin mux register this register is the p d p ort m ode select register , and must be set up correctly before us ing the port to ensure that the port functions as designed. p cd . mr=0x4000_1300 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw p ort selection bit 00 01 10 11 pd 0 pd0 * ss0 t8io pd 1 pd1 * sck0 t9io pd 2 pd2 * m osi0 scl0 pd 3 pd3 * miso0 sda0 p c n . cr port n pin control register (except for pccr) this register controls the i nput or output of each port pin. each pin can be configured as input pin, output pin , or open - drain pin. p c a . cr=0x4000_1004, p c b . cr=0x4000_1 104, p c d . cr=0x4000_1304 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 rw rw rw rw rw rw rw rw rw rw rw rw rw r w rw rw pn port control 00 push - pull output 01 open - drain output 10 input 11 analog
z32f064 1 product specification port control unit ps03440 4 - 0417 preliminary 62 pcccr port c pin control register this register controls the i nput or output of each port pin. each pin can be configured as input pin, output pin , or ope n - drain pin. p c c . cr=0x4000_1204 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 11 11 11 11 10 10 11 11 11 11 11 10 10 00 10 10 rw rw rw rw rw rw rw rw rw rw r w rw rw rw rw rw pn port control 00 push - pull output 01 open - drain output 10 input 11 analog p c n . pcr port n pull - up resistor control register every pin in the port has on - chip pull - up resistors which can be configured by the pnpcr reg is t e rs. p c a . pcr=0x4000_1008, p c b . pcr=0x4000_1108 p c c . pcr=0x4000_1208, p c d . pcr=0x4000_1308 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pue15 pue14 pue13 pue12 pue11 pue10 pue9 pue8 pue7 pue6 pue5 pue4 pue3 pue2 pue1 pue0 0000 rw n puen port pull - up control 0 disable pull - up resistor 1 enable pull - up resister
z32f064 1 product specification port control unit ps03440 4 - 0417 preliminary 63 p c n . der port n debounce enable register every pin in the port has a digital debounce filter which can be configured by the pnder re gister s. . the debounce clock can be configured in the dbclkx r egisters. p c a . der=0x4000_100c, p c b . der=0x4000_110c p c c . der=0x4000_120c, p c d . der=0x4000_130c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pde15 pde14 pde13 pde12 pde11 pde10 pde9 pde8 pde7 pde6 pde5 pde4 pde3 pde2 pde1 pde0 0000 rw pden pin debounce enabl e 0 disable debounce filter 1 enable debounce filter p c n . ier port n interrupt enable register each individual pin can be an external interrupt source. the edge trigger interrupt and level trigger interrupt are both supported. the interrupt mode c an be configured by setting the pnier registers . p c a . ier=0x4000_1010, p c b . ier=0x4000_1110 p c c . ier=0x4000_1210, p c d . ier=0x4000_1310 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pie15 pie14 pie13 pie12 pie11 pie10 p ie9 pie8 pie7 pie6 pie5 pie4 pie3 pie2 pie1 pie0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw pien pin interrupt enable 00 interrupt disabled 01 enable interrupt as level trigger mode 10 res erved 11 enable interrupt as edge trigger mode
z32f064 1 product specification port control unit ps03440 4 - 0417 preliminary 64 p c n . isr port n interrupt status register when an interrupt is delivered to the cpu, the interrupt status can be detected by reading the pnisr register. pnisr register report s a n interrupt source pin and a n interrupt typ e . p c a . isr=0x4000_1014, p c b . isr=0x4000_1114 p c c . isr=0x4000_1214, p c d . isr=0x4000_1314 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pis15 pis14 pis13 pis12 pis11 pis10 pis9 pis8 pis7 pis6 pis5 pis4 pis3 pis2 pis1 pis0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw pisn pin interrupt status 00 no interrupt event 01 low level interrupt or falling edge interrupt event i s present 10 high le vel interrupt or rising edge interrupt event i s present 11 both of rising and falling edge interrupt event is p resent in edge trigger interrupt mode. not available in level trigger interrupt mode
z32f064 1 product specification port control unit ps03440 4 - 0417 preliminary 65 p c n . icr port n interrupt control register this is the interrupt m ode control register. p c a . icr=0x4000_1018, p c b . icr=0x4000_1118 p c c . icr=0x4000_1218, p c d . icr=0x4000_1318 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pic15 pic14 pic13 pic12 pic11 pic10 pic9 pic8 pic7 p ic6 pic5 pic4 pic3 pic2 pic1 pic0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw picn pin interrupt mode 00 prohibit external interrupt 01 low level interrupt or falling edge interrupt mode 1 0 high level interrupt or rising edge interrupt mode 11 both of rising and falling edge interrupt mode. not support for level trigger mode porten port access e n able port access enable provides register writing perm ission for all pcu registers. p orten = 0x4000_ 1ff0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 porten 0 0 0 0 0 0 0 0 -- wo 7 0 porten writing the sequence of 0x15 and 0x51 in this register enables writing to pcu registers, and writing other valu es protects all pcu registers fr om writing.
z32f064 1 product specification port control unit ps03440 4 - 0417 preliminary 66 functional description all the gpio pins can be configured for different operations C inputs, outputs, and triggered interrupts (both level and edge) through the pdu. the system is also able to disable ports by setting the per1 and pcer1 re gisters in the scu. by default , all pins are disabled (except for uart0/spi0) so the developer must enable these to operate. all configuration parameters are protected by the port access enable register. you must write the sequence in order ( 0x15 , 0x51 ) to the porten register to configure any pin(s). once the configuration is complete, write any other value to the porten register to lock it. note: do not read in between the sequence; it will prevent the configuration registers from being unlocked. when the input function of i/o port is used by the pin control r egister, the output function of i/o port is disabled. the port f unction differs acc ording to the pin mux register. the input data register capture s the data present on the i/o pin or d ebounced input da ta at every gpio clock cycle. figure 5 . 4 . port diagram pad vdd diode vss diode 200 ohm vdd vss p - mos n - mos 200 ohm ain5v vdd p - mos pull up register apb de - bounce logic 0 1 r/w demux 00 01 10 11 gpio in func 1 in func 2 in func 3 in pin mux register gpio out func 1 out func 2 out func 3 out 00 01 10 11 de - bounce enable register r/w r/w pin control register r/w control logic input control logic output control logic
z32f064 1 product specification port control unit ps03440 4 - 0417 preliminary 67 figure 5 . 5 . debounce function when the deboun ce function of i nput d ata is used by the debounce enable register , the e xternal input data is captured by the debounce clk. - if cnt value is 01, debounced input data is 1. - if cnt value is 10, debounced input data is 0 the debounce clk of each po rt group can be configured by the dbclk registers. 01 00 11 10 1 external input de - bounced input 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 1 0 1 cnt [1:0] de - bounce clk ff =1 ff =1 ff =1 ff =0 ff =1
z32f064 1 product specification general purpose i/o ps03440 4 - 0417 preliminary 68 6. g eneral p urpose i/o o verview most pins , except the dedicated function pins, can be used as general i/o ports. general input/output ports are controlled by the gpio block. ? output signal level (h/l) sele ct ? input signal level ? output set/clear pin by writing a 1 figure 6 . 1 block d iagram pin d escription table 6 . 1 external s ignal pin name t ype d escription pa io p a0 - pa15 pb io pb0 C pb7 pc io pc0 - pc15 pd io pd0 C pd 3 pcu pnsrr pnodr pnidr pins dout[31:0] d in[31:0] gpio port psel
z32f064 1 product specification general purpose i/o ps03440 4 - 0417 preliminary 69 r egisters the base a ddress of gpio is 0x4000_2000 and the regi ster map is described in table 6 . 2 and table 6 . 3 . table 6 . 2 base a ddress of e ach p ort port address pa port 0x4000_2000 pb port 0x4000_2100 pc port 0x4000_2200 pd port 0x4000_2300 table 6 . 3 gpio register m ap pn . odr port n output data register when the pin is set as output and gpio m ode, the pin output level is defined by pn . odr registers . pa . odr=0x4000_2000, pb . odr=0x4000_2100 pc . odr=0x4000_2200, pd . odr=0x4000_2300 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 odr 0000 rw o dr pin output level 0 output low level 1 output high level pn . idr port n input data register each pin level status can be read in the pn . idr register. even if the pin is a mode other than a nalog m ode, the pin level can be detected in the pnidr re gister. pa . idr=0x4000_2004, pb . idr=0x4000_2104 pc . idr=0x4000_2204, pd . idr=0x4000_2304 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pnidr 0000 ro idr pin current level 0 the pin is low level 1 the pin is high level n ame o ffset t ype d escripti on reset value pn. odr 0x -- 00 rw port n output data register 0x00 000000 pn. idr 0x -- 04 ro port n input data register 0x00 000000 pn.bs r 0x -- 08 wo port n pin set register 0x00 000000 pn.bcr 0x 0c wo port n pin clear register 0x00000000
z32f064 1 product specification general purpose i/o ps03440 4 - 0417 preliminary 70 pn . bsr port n bit set register p n . bsr is a register for control ling each bit of the pnodr register. w rit ing a 1 into the specific bit will set a corresponding bit of pnodr to 1 . writing 0 in this register has no effect. pa . bsr=0x4000_2008, pb . bsr=0x4000_2108 pc . bsr=0x4000_2208, pd . bsr=0 x4000_2308 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bsr 0000 wo bsr pin current level 0 not effect 1 set correspondent bit in pnodr register pn . bcr port n bit clear register pn . brr is a register for control ling each bit of the pnodr register. writing a 1 into the specific bit will set a corresponding bit of pnodr to 0 . writing 0 in this register has no effect. pa.bcr=0x4000_200c, pb.bcr=0x4000_210c pc.bcr=0x4000_220c, pd.bcr=0x4000_230c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pnbcr 0000 wo bcr pin current level 0 not effect 1 clear correspondent bit in pnodr register
z32f064 1 product specification general purpose i/o ps03440 4 - 0417 preliminary 71 functional description the gpio registers provide the input/output condition of the gpio pins. the input data registers give the states of the pins of the ports. th e output data register is for setting the port pins. the set and clear registers control the pins at the individual level. when configured as output, the value written to the gpio ouput data register is output on the i/o pin. when set ting the bit set regi ster, the gpio output data register set s the high. when set ting the bit clr register, the gpio output data register set s the low. the input data register capture s the data present on the i/o pin or d ebounced input data at every gpio c lock cycle. figure 6 . 2 . gpio diagram port control unit apb input data register ( read only ) output data register ( read write ) pad bit set register ( write only ) bit clr register ( write only ) gpio block
z32f064 1 product specification flash memory controller ps03440 4 - 0417 preliminary 72 7. f lash m emory c ontroller introduction the flash memory controller is an internal f lash memory inte rface controller with the following features: ? 64kb flash code memory ? 32 - bit read data bus width ? code cache block for fast access mode ? 128 - byte page size ? support page erase and macro erase ? 128 - byte unit program note : programming the flash requires the execution to occur in ram. once the program mode is selected, flas h is no longer ab le to be read for instructions. table 7 . 1 internal f lash s pecification item de s cription size 64 kb start address 0x0000_0000 end address 0x00 00 _ffff page size 128 - byte total page count 51 2 pages pgm unit 128 - byte erase unit 128 - byte
z32f064 1 product specification flash memory controller ps03440 4 - 0417 preliminary 73 figure 7 . 1 block diagram pin description the flash memory controller has no external interface pins. r egisters the b ase address of the flash memory contr oller is 0x4000_0100 . code flashrom 64 kb ( 16 k x 32bit) register file b u s c o n t r o l m u x ahb bus a p b bus read cache
z32f064 1 product specification flash m emory controller ps03440 4 - 0417 preliminary 74 table 7 . 2 shows the r egister memory map . table 7 . 2 f lash memory controller register m ap n ame o ffset t ype d escription reset value fm . mr 0x0004 rw flash memory mode select register 0x0 1 000000 fm . cr 0x0008 rw flash memory control register 0x 00 000000 fm . ar 0x000c rw flash memory address register 0x00000000 fm . dr 0x0010 rw flash memory data register 0x00000000 fm . tmr 0x0014 rw flash memory timer register 0x00000 0bb fm . drty 0x0018 rw flash memory dirty bit fm . tick 0x001c r o flash memory tick timer 0x00000000 fm . crc 0x0020 ro flash memory read crc value fm. b oot cr 0x00 74 rw boot rom remap clear register 0x 00000000 fm. prot 0x00 78 rw flash page protection regis ter 0x00000000 fm. jtagen 0x00 7c rw jtag protection register 0x00000001 fm . mr flash memory mode register the flash memory mode register is an i nternal f lash memory m ode 32 - bit register . fm . mr=0x4000_0104 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 boot idle verify ambaen trmen trm femod fmod acode 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00 r r r w r w r w r w r r rw 31 boot 0 1 boot mode enable status(read only) 2 4 idle 0 1 boot mode enable status(read only) 23 verify 0 1 flash verify mode enable status(read only) 22 ambaen 0 amba mode disable 1 amba mode enable (can change wait state and etc) 17 trmen 0 1 trim mode entry status(read only) 16 trm 0 1 trim mode status(read only) 9 femod 0 1 flash mode entry status(read only) 8 f mod 0 1 flash mode status(read only) 7 0 acode 5a ? a5 flash mode a5 ? 5a trim mode
z32f064 1 product specification flash memory controller ps03440 4 - 0417 preliminary 75 fm . cr flash memory control register the flash memory control regist er is an i nternal f lash memory control register . fm.cr=0x4000_0108 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 timer test1 test0 vppout ever pver otp b e otp a e ppgm ae pmod we pbld pgm ers pbr 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rw r w rw rw rw rw rw rw rw rw rw rw r rw rw rw rw rw rw rw rw rw rw rw 20 timer 0 program/erase timer enable (timer can be enable by pgm or ers bit) 1 17 16 test 00 normal operati on 01 (read) row voltage mode 01 (write) odd row program 10 even row program 11 all row program 15 vppout enable charge - pump vpp output 14 ever set erase verify mode 13 pver set program verify mode 11 otpbe otp area b enable 10 otpae otp area a enable 9 ppgm pre pgm enable page buffer set automatically 8 ae all erase enable 5 pmode pmode enable(address path changing) 4 we write enable 3 pbld page buffer load(we should be set) 2 pgm program enable 1 ers 0 program mode enab le 1 erase mode enable 0 pbr page buffer reset
z32f064 1 product specification flash memory controller ps03440 4 - 0417 preliminary 76 fm . ar flash memory address register the flash memory address register is an i nternal f lash memory program , erase address register . fm.ar=0x4000_010c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 faddr 0 0x0000 rw 1 3 0 faddr 16k words address (one word = 4 bytes) fm . dr flash memory data register this is an i nternal f lash memory program data register . fm.dr=0x4000_0110 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fdata 0x0000_0000 rw 31 0 fdata flash pgm data (32 - bit) fm . tmr flash memory timer register the flash memory timer register is an i nternal f lash memory timer value register ( 16 - bit) . erase/program timer runs up to tmr[ 15 :0 ] fm.tmr=0x4000_011 4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr 0x09c4 rw 7 0 tmr erase/pgm timer (default, 0x09c4) timer counts up to tmr[15:0] by 1mhz int. osc cloc k or external osc clock. it can be selected in tmr ck bit.
z32f064 1 product specification flash memory controller ps03440 4 - 0417 preliminary 77 fm . drty flash memory dirty b it register this is an i nternal f lash memory dirty bit clear ing register . fm.drty=0x4000_0118 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fdrty - write only 31 0 fdrty write any value here, cache line fill flag will be clear ed. note: this device has a small internal cache. all cache lines are cleared when any data is written to this register. fm . tick flash memory tick timer r egister the flash memory tick timer register is an i nternal f lash memory burst mode channel selection register . fm.tick=0x4000_011c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ftick 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000 rw 17 0 ftick tick goes to 0x3ffff from written tick value while t rm runs by pclk clock fm . crc flash memory crc v alue r egister the flash memory crc value register is t he c yclic r edundancy c heck (crc) value resul ting from read access on internal f lash memory . fm.crc=0x4000_0120 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 crc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xffff ro 15 0 crc crc16 value
z32f064 1 product specification flash memory controller ps03440 4 - 0417 preliminary 78 fm . cfg flash memory c onfig v alue r egister the flash memory config value register is t he f lash configuration register. fm.cfg=0x4000_0130 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 write key hrespd tmrck wait crcinit crcen trim 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 rw 31 15 write key key value : 0x7858 15 hrespd disable hresp(erro r response function) of data or system bus (hresp is amba ahb signal) 12 tmrck 0 pgm/erase timer source is 1mhz ringosc prm/erase timer source is external clock 10 8 wait 000 no wait access for flash memory 001 1 - wait inserted for flash access 010 2 - wait inserted for flash access 011 3 - wait inserted for flash access 7 crcinit 0 1 crc register winll be i nitialized. it should be reset a gain before read flash to generate crc16 calculation (initial value of fmcrc is 0xffff) 6 crcen 0 crc16 enable crc value will be calculated at every flash read timing 1 3 0 trim flash trim value (trim_mode_entry) fm. b oot cr boot rom remap clear register this is the boot rom remap clear register . this register is an 8 - bit register. fm.bootcr=0x4000_0174 7 6 5 4 3 2 1 0 bootrom 0 0 0 0 0 0 0 1 r 0 bootrom boot mode (only can be written in boot loader mode) this bit is used to clear boot loader mode at end of boot code (when bootrom low, external boot pin si gnal is masked)
z32f064 1 product specification flash memory controller ps03440 4 - 0417 preliminary 79 fm. protect write protection control register the write protection control register is an i nternal f lash memory control register . fm .protect= 0x4000_0178 31 30 29 28 27 26 25 24 2 3 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 write_key wp15 wp14 wp13 wp12 wp11 wp10 wp9 wp8 wp7 wp6 wp5 wp4 wp3 wp2 wp1 wp0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 w p 15 0xf000 ~ 0xffff , write_key is 0x87 14 wp14 0xe000 ~ 0xefff , write_key is 0x87 13 wp13 0xd000 ~ 0xdfff , write_key is 0x87 12 wp12 0xc000 ~ 0xcfff , write_key is 0x87 11 wp11 0xb000 ~ 0xbfff , write_key is 0x87 10 wp 10 0xa000 ~ 0xafff , write_key is 0x87 9 wp9 0x9000 ~ 0x9fff , write_key is 0x87 8 wp8 0x8000 ~ 0x8fff , write_key is 0x87 7 wp7 0x7000 ~ 0x7fff , write_key is 0x87 6 wp6 0x6000 ~ 0x6fff , write_key is 0x87 5 wp5 0x5000 ~ 0x5fff , write_key is 0x87 4 wp4 0x4000 ~ 0x4fff , write_key is 0x87 3 wp3 0x3000 ~ 0x3fff , write_key is 0x87 2 wp2 0x2000 ~ 0x2fff , write_key is 0x87 1 wp1 0x1000 ~ 0x1fff , write_key is 0x98 0 wp0 0x0000 ~ 0x0fff , write_key is 0x98 fm.jtagen jtag protection control registe r the jtag protection control register is a d ebug access control register . fm .jtagen =0x4000_017c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 write_key jtagen 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 rw 0 jtagen 0 1 debug access port is disabled, write access code is 0xc7 debug access port is enabled
z32f064 1 product specification flash memory controller ps03440 4 - 0417 preliminary 80 functional description flash memory controller is an internal f lash memory interf ace controller. it mainly controls the program f las h memory operation and prepares read data for requesting from the bus. flash organization the 64 kbytes code f lash memory c onsists of 1,024 pages which have a uniform 128 - bytes page size. the f lash control ler allows for read ing or writing a data of the f lash memory. r ead a c cess can be performed by 8, 16 , and 32 bits wide . this momory is located at 0x0000_0000 address on the system memory map. the system boot address is 0x0000_0000 , so this f lash memory is b oot memory. the code data which is programmed in the f lash memory will boot up the device after the boot rom sequence is completed . flash read operation the f lash data read operation is requested from the bus. the f lash controller responds to the request b y itself. the wait time should be correctly defined b ecause the bus speed is usually faster than f lash data access time. the normal read operation is not available in flash mode in the acode.fm.mr field. flash program operation the erase and program access of f lash memory is available only in flash mode in the acode.fm.mr field. therefore , self - program ming is not supported. the f lash program/erase operation should be performed by the execut ion program on the sram memory. the flash program operation write s o ne page to the target address selected by the fm.ar register. at fir s t, user s should write the program data into the page buffer. page buffer write is pefromed by word write access to the fm.dr register on the fm.ar address. after fill ing the page buffer, user s can start the f lash write operation and should wait for the idle bit to be set. figure 7 . 2 s hows the page buffer loading operation. figure 7 . 2 . pa ge buffer load timing diagram the f lash write of page buffer data is performed by the prgm.fm.cr command. s afe writing operation requires correct program time. the program time tpgm is defined by the fm.tmr register. this timer count s the number of hclk c lock to the fm.tmr value. when the timer count starts , the idle.fm.mr register is cleared. when t he timer count is completed, the idle.fm.mr register is set. in this page write operation, the target page address should be written in the fm.ar register.
z32f064 1 product specification flash memory controller ps03440 4 - 0417 preliminary 81 figure 7 . 3 sh ows the page write operation. figure 7 . 3 .page erase timing diagram the f lash erase of page data is done by the ers.fm.cr command. s afe writing operation requires correct program tim e. the erase time ters is defined by the fm.tmr register. this timer count s the number of hclk clock to the fm.tmr value. when the timer count starts , the idle.fm.mr register is cleared. when t he timer count is completed, the idle.fm.mr register is set. figure 7 . 4 shows the bulk erase operation. figure 7 . 4 . bulk erase timing diagram
z32f064 1 product specification internal sram ps03440 4 - 0417 preliminary 82 8. i nternal sram o verview the z32f064 1 mcu has a block of 0 - wait on - chip sr am. the size of sram is 8 kb. the sram base address is 0x2000_0000 . the sram memory area is usually used for data memory and stack memory. sometimes the code is dumped into the sra m memory for fast operation or f lash erase/ pgm operation. this device does n ot support a memory remap strategy; therefore, jump and return is required to execute the code in the sram memory area. figure 8 . 1 sram block d iagram code flash (64kb) sram (8kb) 0x0000_0000 0x0000_ffff 0x2000_0000 0x2000_1fff
z32f064 1 product specification direct memory access controller ps03440 4 - 0417 preliminary 83 9. d irect m emory a ccess c ontroller introduction features of the direct m emory a ccess c ontroller (dmac) include: ? four c hannel s ? single transfer only ? support s 8/16/32 - bit data size ? support s multiple buffer s with same size ? interrupt condition is transferred through peripheral interrupt a block diagram of the dmac i s shown in figure 9 . 1 . figure 9 . 1 block diagram pin d escription the dmac has n o external interface pins .
z32f064 1 product specification direct memory a ccess controller ps03440 4 - 0417 preliminary 84 r egisters the b ase addr ess of the dma controller is shown in table 9 . 1 . table 9 . 1 dma controller b ase a ddress c hannel base address dmach0 0x4000_0400 dmach1 0x4000_0410 dmach2 0x4000_0420 dmach3 0x4000_0430 table 9 . 2 shows the register map of the dma controller . table 9 . 2 dmac register m ap name offset type description reset value dc n . cr 0x0000 rw dma channel n control register 0x 0000_ 0000 dc n . sr 0x0004 rw dma channel n status register 0x 0000_0000 dc n . par 0x0008 r dma channel n peripheral address 0x 0000_0000 dc n . mar 0x000c rw dma channel n memory address 0x2000_0000 dc n . cr dma controller configuration register this dma operation co ntrol register is a 32 - bit register. dc0 . cr=0x4000_0400 , dc1 . cr=0x4000_0410 dc2 . cr=0x4000_0420 , dc3 . cr=0x4000_0430 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 transcnt perisel size dir 0 0 0 0 0x000 0 0 0 0 0 0 0 0 0 00 0 0 rw rw rw rw 27 16 transcnt number of dma transfer remained required transfer number should be written before ena ble dma transfer. 0 dma transfer is done. n n transfers are remained 11 8 perisel peripher al selction n associated peripheral selection. refer to dma peripheral connection table 3 2 size bus transfer size. 00 dma transfer is byte size transfer 01 dma transfer is half word size transfer 10 dma transfer is word size transfer 11 r eserved 1 dir select transfer direction. 0 transfer direction is from memory to peripheral. (t x) 1 transfer direction is from peripheral to memory (r x)
z32f064 1 product specification direct memory access controller ps03440 4 - 0417 preliminary 85 a dma channel is connected to the selected peripheral. table 9 . 3 sh ows the peripheral sel e ction s . this perisel field must be configured with the correct number of peripheral s that will be connected to the dma interface. table 9 . 3 dmac perisel selection perisel[3:0] associat ec peipheral 0 channel idle 1 uart0 rx 2 uart0 tx 3 uart1 rx 4 uart1 tx 5 spi0 rx 6 spi0 tx 7 adc0 rx 8 adc1 rx 9 - 15 n . a . note: perisel can not have the same value in different channels. if the same perisel value is wriiten in more than one ch annel, proper operation is not guaranteed . unused channel s must contain channel idle value in perisel bit postions. dc n . sr dma controller status r egister the dma controller status register is an 8 - bit register. this register represents the current status of the dma controller and enables dma function. dc0 . sr=0x4000_0404 , dc1 . sr=0x4000_0414 dc2 . sr=0x4000_0424 , dc3 . sr=0x4000_0434 7 6 5 4 3 2 1 0 eot dmaen 1 0 0 0 0 0 0 0 ro rw 7 eot end of transfer. 0 data to be transferred is exist ing . transcnt shows non zero value 1 all data is transferred. transcnt shows now 0 0 dmaen dma enable 0 dma is in stop or hold state 1 dma is running or enabled
z32f064 1 product specification direct memory access controller ps03440 4 - 0417 preliminary 86 dc n . par dma controller peripheral address r egister this register represent s the peripheral address es . dc0 . par=0x4000_0408 , dc1 . par=0x4000_0418 dc2 . par=0x4000_0428 , dc3 . par=0x4000_0438 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 peripheral base offset par 0x4000 0x0000 ro rw 31 0 par target peripheral address of transmit buffer or receive buffer. user must set exact target peripheral buffer address in this field. if dir is 0 this ad dress is destination address of data transfer. if dir is 1, this address is source address of data t ransfer. dc n . mar dma controller memory address r egister this register represent s the memory address es . dc0 . mar=0x4000_040c , dc1 . mar=0x4000_041c dc2 . mar=0x4000_042c , dc3 . mar=0x4000_043c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mar 0x2000 0x0000 ro rw 31 0 mar target memory address of data transfer. address is automatically incremented according to size bits when each transfer is done. if dir is 0 this address is source address of da if dir is 1, this address is destination address of dat
z32f064 1 product specification direct memory access controller ps03440 4 - 0417 preliminary 87 functi onal d escription the dma controller performs direct memory transfer by sharing the system bus with the cpu core. the system bus is shared by 2 ahb masters following the round - robin priority strategy. therefore, the dma controller can share half of the system bandwidth. the dma controller is triggered only with a peripheral request. wh en a peripheral request s the transfer to the dma controller, the associated channel is activate d and access es the bus to transfer the requested data from memory to the peripheral data buffer or from the peripheral data buffer to memory space. 1. user set s the peripheral address and memory address . 2. user configure s dma op eration mode and trans fer count . 3. user enable s the dma channel . 4. peripheral sends a dma reques t . 5. dma activate s the channel that was requested . 6. dma read s data from the source address and save s it to the internal buffer . 7. dma write s the buffered data to the destination address . 8. tran sfer count number is decreased by 1 . 9. when transfer count is 0, the eot flag is set and a notice sent to peripheral to issue the interrupt . 10. dma does not have an interrupt source; the interrupt related dma status can be shown from the assigned peripheral int errupt. figure 9 . 2 . block diagram figure 9 . 2 shows the functional timing diagram of the dma controller. the transfer request from the peripheral is pen ded internally and it invoke s source data read transfer on the ahb bus. the read data from the source address is stored in the internal buffer. t his data will then be transferred to the destination address when the ahb bus is available. the timing diagram for a dma transfer from the peripheral to memory is shown in figure 9 . 3 . a 4 - clock cycle latency exists when accessing the peripheral. if the bus is occupied by a different bus master, the number of bus waiting cycles increase unt il the bus is available .
z32f064 1 product specification direct memory access controller ps03440 4 - 0417 preliminary 88 figure 9 . 3 . dma transfer from peripheral to memory the timing diagram for a dma transfer from memory to the peripheral is shown in figure 9 . 4 . 4 - clock cycle latency exists during accessing the peripheral. if the bus is occupied by a different bus master, there are amount of bus waiting cycles. figure 9 . 4 . dma transfer from memory to peripheral the figure is an example n data transfers with the dma. the dma transfer is started when dcnsr.dmaen is set and will be cleared when all the number of transfer is completed. figure 9 . 5 . n dma transfer example
z32f064 1 product specification watchdog timer ps03440 4 - 0417 preliminary 89 10. w atchdog t imer o verview the watchdog timer can monitor the system and generate an interrupt or a reset. it has a 32 - bit down - counter. the miscellaneous clock control register 3 prov ides base clock options with clock dividers to drive the wdt clock. this can be selected in the wdtcon register. to prevent the wdt from firing, reload the lr register with the appropriate value before the wdt times out. 32 - bit down counter (wdtcvr) featur es include: ? select reset or periodic interrupt ? count clock selection ? dedicated pre - scaler ? watchdog overflow output signal figure 10 . 1 block diagram
z32f064 1 product specification watchdog timer ps03440 4 - 0417 preliminary 90 r egisters the base a ddress of the watchdog timer is 0x40 00_0200 and the register map is described in table 10 . 1 . the i nitial watchdog time - out period is set to 2 , 000 - milisecond s . table 10 . 1 watchdog t imer r egister m ap name offset type desc ription reset value wdt . lr 0x0000 w wdt load register 0x00000000 wdt . c nt 0x0004 r wdt current counter register 0x0000ffff wdt . con 0x0008 rw wdt control register 0x0000 8 05c wdt . lr watchdog timer load register the wdtlr register is used to update the wd tcvr register . to update the wdtcvr register, the wen bit of wdtcon should be set to 1 and writ ten to the wdtlr register with a target value of wdtcvr. wdt . lr=0x4000_0200 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wdtlr 0x0000_0000 rw 31 0 wdtlr watchdog timer load value register keeping wen bit as 1, write wdtlr register will upd wdt . c nt watchdog timer current count er register the wdtc nt register represent s the curren t count value of 32 - bit down counte r .when the counter value reach es 0, an inte rrupt or reset occurs . wdt . lr=0x4000_0204 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wdt cnt 0x0000_ ffff rw 31 0 wdtcnt watchdog timer current counter register 32 - bit down counter will run from the written value.
z32f064 1 product specification watchdog timer ps03440 4 - 0417 preliminary 91 wdt . con watchdog timer control register wdt module should be configured properly before running. when target purpose is defined, the wdt can be configured in the wdt co n register wdt . con=0x4000_0208 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wdbg wuf wdtie wdtre wdten cksel wprs 1 0 0 0 0 0 0 0 0 1 0 1 1 1 00 rw rw rw rw rw rw rw 15 wd bg watchdog operation control in debug mode 0 watchdog counter running when debug mode 1 watchdog counter stopped when debug mode 8 wuf watchdog timer underflow flag 0 no underflow 1 underflow is pending 7 wdtie watchdog timer counter underflow interrupt enable 0 disable interrupt 1 enable interrupt 6 wdtre watchdog timer counter underflow interrupt enable 0 disable reset 1 enable reset 4 wdten watchdog counter enable 0 watch dog counter disabled 1 watch dog counter enabled 3 cksel wdtclkin clock source select 0 pclk 1 external cloc k ( ringosc 1mhz ) 2 0 wprs counter clock prescaler wdtclk = wdtclkin/wprs 00 0 wdtclkin 0 0 1 wdtclkin / 4 0 10 wdtclkin / 8 011 wdtclkin / 16 100 wdtclkin / 32 101 wdtclkin / 64 110 wdtclkin / 128 1 11 wdtclkin / 256
z32f064 1 product specification watchdog timer ps03440 4 - 0417 preliminary 92 functional de scription the watchdog timer c ount can be enabled by setting wdten (wdt.con[4]) to 1. when the watchdog timer is enabled, the down counter s tart s counting from the load value. if wdtre (wdt.con[6]) is set as 1, wdt reset will be asserted wh en the wdt count er value reaches 0 (underflow event) from the wdtlr value. before wdt counter goes down to 0, the software can write a certain value to the wdtlr register to reload the wdt counter. timing diagram figure 10 . 2 . timing diagram in interrupt mode operation when wdt clock is the external clock in wdt i nterrupt mode, after wdt underflow occurs, a certain count value is reloaded to prevent the next wdt interrupt in a short time period and this reloading action can only be activated when the watchdog timer counter is set to interrupt mode (set wdtie of wdt.con). it takes up to 5 cycle s from the load value to the cnt value. the wdt interrupt signal and the cnt value data might be delayed by a maximum of 2 system bus clocks in synchronous logic. prescale table the watchdog timer includes a 32 - bit down counter with programmable pre - scaler to defin e different time - out intervals. the clock sources of watchdog timer can be peripheral clock (pcl k) or one of 3 external clock sources. the e xternal clock source can be enable d by cksel (wdt.con[3]) set to 1 . the e xternal clock source is selected in the mccr3 register of the system c ontrol u nit block. to make the wdt counter base clock, user s can co ntrol the 3 - bit pre - scaler wprs [2:0] in the wdt.con register and the maximum pre - scaled value is clock source frequency/256. the pre - scaled wdt counter clock frequency values are listed in table 10 . 2 . selectable clock source (4 0 khz ~ 16 mhz) and the time out interval when 1 count time out period = {(load value) * (1/pre - scaled wdt counter clock frequency) + max 5t ext } + max 4t clk *time out period (time out period from load value to interrupt set 1)
z32f064 1 product specification watchdog timer ps03440 4 - 0417 preliminary 93 table 10 . 2 . pre - scaled wdt counter clock frequency clock source wdtclkin wdtclkin /4 w d t c l kin/8 w d t c l kin/16 w d t c l kin/32 w d t c l kin/64 w d t c l kin/128 w d t c l kin/256 ring osc 1mhz 250khz 125khz 62.5khz 31.25khz 15.625khz 7.8125khz 3.90625kh z mclk mclk (bus clk) mclk/4 mclk/8 mclk/16 mclk/32 mclk/64 mclk/128 mclk/256 eosc xtal xtal/4 xtal/8 xtal/16 xtal/32 xtal/64 xtal/128 xtal/256
z32f064 1 product specification 16 - bit timer ps03440 4 - 0417 preliminary 94 11. 16 - b it t imer o verview the timer block consists of six channels of 16 - bit g eneral - purpose timer s . they supp ort periodic timer, pwm pulse, one - shot timer , and capture mode . the 16 - bit timer has the following features: ? 16 - bit up - counter ? periodic timer mode ? o ne - shot timer mode ? pwm pulse mode ? capture mode ? 10 - bit prescaler ? synchronous start and clear function figure 11 . 1 shows the block diagram of a unit timer block. figure 11 . 1 block d iagram
z32f064 1 product specification 16 - bit timer ps03440 4 - 0417 preliminary 95 pin d escription table 11 . 1 external p in p in name t ype d escription tn io i external clock/ capture input and pwm/one - shot output r egisters the base a ddress of the timer is 0x4000_3000 and the register map is described in table 11 . 3 . table 11 . 2 base a ddress of e ach c hannel channel b ase address t0 0x4000_3000 t1 0x4000_3 0 20 t2 0x4000_3 040 t3 0x4000_3 060 t8 0x4000_3 1 00 t9 0x4000_3 12 0 table 11 . 3 timer r egister m ap n ame o ffset t ype d escription reset value t n . c r1 0x -- 00 rw timer control register 1 0x00 000000 t n . cr2 0x -- 0 4 rw timer control register 2 0x00 000000 t n . prs 0x -- 08 rw timer prescaler register 0x00 000000 t n . gra 0x -- 0c rw timer general data register a 0 x00 000000 t n . grb 0x -- 10 rw timer general data register b 0x00 000000 t n . cnt 0x -- 14 rw timer counter register 0x00 000000 t n . s r 0x -- 18 rw timer status register 0x00 000000 t n . ier 0x -- 1c rw timer interrupt enable register 0x00 000000
z32f064 1 product specification 16 - bit timer ps03440 4 - 0417 preliminary 96 tn . c r1 timer n contro l register 1 the timer control register 1 is a 16 - bit register. the t imer module should be accurately configured prior to operating it . when a target purpose is defined, the timer can be configured in the tncr1 register . t0 . cr1= 0x4000_3000 , t1 . cr1=0x4000_3 020 t2 . cr1=0x4000_3040, t3 . cr1=0x4000_3060 t8 . cr1=0x4000_3 1 00, t9 . cr1=0x4000_3 12 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssync csync uao outpol adctrgen start lvl cksel clrmod mode 0 0 0 0 0 0 0 0 0 000 00 00 rw rw rw rw rw rw rw rw 15 ssync sy nchronize start counter with other synchronized timer s 0 single counter mode 1 synchronized counter start mode 14 csync synchronize clear counter with other synchronized timer s 0 single counter mode 1 synchronized counter clear mode 13 uao select gra, grb update mode 0 writing gra or grb takes effect after current period 1 writing gra or grb takes effect in current peri od 12 outpol timer output polarity 0 normal output 1 negated output 8 adctrgen adc trigger enable control 0 disable adc trigger 1 enable adc trigger 7 startlvl timer output polarity control 0 default output level is high 1 defulat output level is low 6 4 cksel[2:0] counter clock source select 000 pclk/2 001 pclk/4 010 pclk/16 011 pcl k/64 10x mccr3 clock setting 11x tnio pin input (tnio pin must be set as input mode) 3 2 clrm o d clear select when capture mode 00 rising edge clear mode 01 falling edge clear mode 10 both edge clear mode 11 none clear mode 1 0 mode time r operation mode control 00 normal periodic operation mode 01 pwm mode 10 one shot mode 11 capture mode
z32f064 1 product specification 16 - bit timer ps03440 4 - 0417 preliminary 97 tn . c r2 timer co ntrol register 2 the timer control register 2 is an 8 - bit register. t0 . cr2=0x4000_3004, t1 . cr2=0x4000_3024 t2 . cr2=0x4000_3 044, t3 . cr2=0x4000_3064 t8 . cr2=0x4000_3 10 4, t9 . cr2=0x4000_3 12 4 7 6 5 4 3 2 1 0 tclr ten 0 0 0 0 0 0 0 0 r r r r r r w o rw 1 tclr timer register clear 0 normal operation 1 clear count register. (this bit will be cleared after next timer c lock) 0 ten timer enable bit 0 stop timer counting 1 start timer counting note: it is recommended that the timer is started with tclr bit setting at 1 . tn . prs timer n prescale r register the timer prescaler register is a 16 - bit register designed to pr e scale the counter input clock. t0 . prs=0x4000_3008, t1 . prs=0x4000_3028 t2 . prs =0x4000_3048, t3 . prs=0x4000_3068 t8 . prs=0x4000_3 1 08, t9 . prs=0x4000_3 12 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 prs 0 0 0 0 0 0 000 rw 9 0 prs pre - scale value of count clock tclk = clock_in/(prs+1) ( clock_in is a selected timer input clock)
z32f064 1 product specification 16 - bit timer ps03440 4 - 0417 preliminary 98 tn . gra timer general register a the t imer gen eral register a is a 16 - bit register . t0 . gra=0x4000_300c, t1 . gra=0x4000_302c t2 . gra =0x4000_304c, t3 . gra=0x4000_306c t8 . gra=0 x4000_3 1 0c, t9 . gra=0x4000_3 12 c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gra 0x00 00 rw 15 0 gra general register a (duty/interrupt register) periodic mode / pwm / one - shot mode - in pwm mode this register is used as duty value. - when the counter valu e is matched with this value, gra match interrupt is requested capture mode - falling edge of tnio port will capture the count valu e when rising edge clear mode - rising edge of tnio port will capture the count value when falling edge clear mode tn . gr b timer n general register b the timer general register b is 16 - bit register . t0 . grb=0x4000_3010, t1 . grb=0x4000_3030 t2 . grb=0x4000_3050, t3 . grb=0x4000_3070 t8 . grb=0x4000_3 11 0, t9 . grb=0x4000_3 13 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 grb 0x0000 rw 15 0 grb general register b (period register) periodic mode / pwm / one - shot mode - in periodic mode or pwm mode, this register is used as period value. the counter will count up to (grb - 1) value. - when the counter value is matched with this value, grb ma tch interrupt is requested only in pwm and on e - shot modes. capture mode - rising edge of tnio port will capture the count value when rising edge clear mode - falling edge of tnio port will capture the count value when falling edge clear mode
z32f064 1 product specification 16 - bit timer ps03440 4 - 0417 preliminary 99 tn . cnt timer count register. the timer count register is a 16 - bit register. t0 . cnt=0x4000_3014, t1 . cnt=0x4000_3034 t2 . cnt=0x4000_3054, t3 . cnt=0x4000_3074 t8 . cnt=0x4000_3 11 4, t9 . cnt=0x4000_3 13 4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cnt 0x0000 rw 15 0 cnt tim er count value register r read current timer count value w set count value tn . s r timer n status register the timer s t atus register is an 8 - bit register. this register indicates t he current status of timer module . t0 . sr=0x4000_3018, t1 . sr=0x4000_30 38 t2 . sr=0x4000_3058, t3 . sr=0x4000_3078 t8 . sr=0x4000_3 11 8, t9 . sr=0x4000_3 13 8 7 6 5 4 3 2 1 0 mfa mfb ovf 0 0 0 0 0 0 0 0 rw rw rw 2 mfa gra match flag 0 no direction change 1 match flag with gra 1 mfb grb match flag 0 no direction change 1 match flag with grb 0 ovf counter overflow flag 0 no direction change 1 counter overflow flag note: t he ovf flag occurs only when the counter rolls from 0xffff to 0 .
z32f064 1 product specification 16 - bit timer ps03440 4 - 0417 preliminary 100 tn . i er timer interrupt enable register the timer interrupt enable register is an 8 - bit register. each status flag of the timer block can issue the interrupt. to enable the interrupt, write 1 in the corresponding bit in the tni e r register. t0 . ier=0x4000_301c, t1 . ier=0x4000_303c t2 . ier=0x4000_305c, t3 . ier=0x4000_307c t8 . ie r=0x4000_3 11 c, t9 . ier=0x4000_3 13 c 7 6 5 4 3 2 1 0 ma ie mb ie ov ie 0 0 0 0 0 0 0 0 w rw w 2 maie gra match interrupt enable 0 not effect 1 enable match register a interrupt 1 mbie grb match interrupt enable 0 not effect 1 enable match register b interrupt 0 ovie counter overflow interrupt enable 0 not effect 1 enable counter overflow interrupt
z32f064 1 product specification 16 - bit timer ps03440 4 - 0417 preliminary 101 functional description timer basic operation in figure 11 . 2 , tmclk is a reference clock for operation of the timer. when t his clock is divided by the prescaler setting , the counting clock will work. figure 11 . 2 . basic start and match operation the period of timer count can be cal culated as shown in the following equation: the perio d = tmclk period * tn.grb value match a interrupt tim e = tmclk period * tn.gra value if the tn.cr1.uao bit is 0, the tn.cr2.tclr command will initialize all the registers in the timer block and load th e gra and grb value s into the data0 and data1 buffer. when you change the timer setting and restart the timer with the new setting, it i s recommended that you write the cr2.tclr command before the cr2.ten command. (a) timer initialization is pe rformed by the tclr command and the timer is started by the ten command. (b) timer is reset by match ing grb timing and count ing again from 00 .
z32f064 1 product specification 16 - bit timer ps03440 4 - 0417 preliminary 102 the update timing of the data0 and data1 buffer in dynamic operation is differ ent in each operating mode and depends on the tn.cr1.uao bit. normal periodic mode figure 11 . 3 shows the timing diagram in normal periodic mode. tn.grb value decides the timer period. one more compare point is provided with tn.gra register value. figure 11 . 3 . normal periodic mode operation the p e riod of timer count can be calculated as shown in the following equation: the perio d = tmclk period * tn.grb value match a interrupt tim e = tmclk period * tn.gra value if tn.grb = 0, the timer can not be started even if tncr2.ten is 1 because the pe riod is 0. the value in tn.gra and tn.grb is loaded into the internal compar e data buffer s 0 and 1 when the loading condition occurs . in this periodic mode with tncr1.uao =0, the tn.cr2. tclr write operation and the grb match event will load the compare data buffer s . when tncr1.uao is 1, the internal compare data buffer is updated whenever the tn.gra or tn.grb data is updated. the tnio output signal will be toggled at every match a condition time. if the value of tngra is 0 , the tnio output does not change it s previous level. if tngra is the same as tngrb, the tnio ouput will toggle at same time as the counter start time. the initial level of the tnio signal is decided by the tncr1.startlvl value. one shot mode figure 11 . 4 shows the timing diagram in one shot mode. tn.grb value decides the one shot period. one more compare point is provided with tn.gra register value.
z32f064 1 product specification 16 - bit timer ps03440 4 - 0417 preliminary 103 figure 11 . 4 . one shot mode operation the period of one shot count can be calculated as shown in the following equ ation: the perio d = tmclk period * tn.grb value match a interrupt tim e = tmclk period * tn.gra value if tn.grb = 0, the timer can not be started even if tncr2.ten is 1 because the pe riod is 0. the value in tn.gra and tn.grb is loaded into the internal compare data buffer 0 and 1 when the loading condition occurs . in this periodic mode with tncr1.uao =0, the tn.cr2.tclr write operation and the grb match event will load the compare data buffers. when tncr1.uao is 1, the internal compare data buffer is upd ated whenever the tn.gra or tn.grb data is updated. the tnio output signal format is the same as pwm mode. tn.grb value defines the output pulse period and the tn.gra value defines the pulse width of one shot pulse. pwm timer output figure 11 . 5 shows the timing diagram in pwm output mode. the tn.grb value decides the pwm pulse period. an additional comparison point is provided by the tn.gra register value which defines the pulse width of pwm output.
z32f064 1 product specification 16 - bit timer ps03440 4 - 0417 preliminary 104 figure 11 . 5 . pwm output operation the period of pwm pulse can be calculated as shown in the following equation: the period = tmclk period * tn.grb value match a interrupt time = tmclk period * tn.gra value if tn.grb = 0, the timer can not be started even tncr2.ten is 1 b ecause the period is 0. the value in tn.gra and tn.grb is loaded into the internal compare data buffer 0 and 1 when the loading condition occurs . in this periodic mode with tncr1.uao =0, the tn.cr2.tclr write operation and the grb match event will load the compare data buffers. when tncr1.uao is 1, the inter n al compare data buffer is updated whenever the tn.gra or tn.grb data is updated. the tnio output signal generates a pwm pulse. the tn.grb value defines the output pu lse period and the tn.gra value defines the pulse width of one shot pulse.the active level of the pwm pulse can be control led by the tn.cr1.startlvl bit value. adc trigger generation is available at match a interrupt time.
z32f064 1 product specification 16 - bit timer ps03440 4 - 0417 preliminary 105 pwm synchronization function 2 - pwm outputs are usually used as synchronous pwm signal control. this function is provided with a synchronous start function. figure 8.6 shows the synchronous pwm generation function. figure 11 . 6 . example of timer synchronization function ( ssync=0) t0.cnt t0io output t1io output t1.grb t1.gra t0.cr2 ten=1 (ssync=0) t1.cnt=t1.gra t0.cnt=t0.gra t0.grb t 0.gra t1.cr2 ten=1 (ssync=1) t1.cnt timer0 was cleared by start event of timer1 (ssync=1) timer0 restarts timer0 starts timer1 starts
z32f064 1 product specification 16 - bit timer ps03440 4 - 0417 preliminary 106 figure 11 . 7 . example of timer synchronization function (csync=1) the tncr1.ssync bit controls start sync hronization with other t imer blocks. the tncr1.csycn bit controls clear sync with other timer blocks. the ssync and csync bits are only effective when used with two or more timers. for example, timer0 and timer1 set the ssync and ccsync bit s in each cr1 register ; both timers are started whenever one of them is enabl ed and b oth timers will cleared with a short period match value. however, others are not affected by these two timers, and they can be operated independently because their sync control bit is 0. capture mode figure 11 . 8 shows the timing diagram in the capture mode operation. the tnio input signal is used for capturing the pulse.rising and falling edges can capture the counter value in each capture codition.
z32f064 1 product specification 16 - bit timer ps03440 4 - 0417 preliminary 107 figure 11 . 8 . capture mode operation a 5 pclk clock cycle is required internally. therefore, the actu al capture point is after 5 pclk clock cycles from the rising or falling edge of the tnio input signal. the in tern al counter can be cleared in multiple mode s . the tncr1.clrmd field controls the counter clear mode. the following clear modes are supported: r ising edge , falling edg e , both edge s, and none . the example in figure 11 . 8 is of rising edge clear mode. adc trigger function the t imer module can generate adc start trigger signals. one timer can be one trigger source of the adc block. trigger source control is performed by the adc control register. figure 11 . 9 show s the adc trigger function. the conversion rate must be shorter than the timer period, else an overrun situation can occur . a dc acknowledge is not required because the trigger signal is automatically cleared after 3 pclk clock pulses.
z32f064 1 product specification 16 - bit timer ps03440 4 - 0417 preliminary 108 figure 11 . 9 . adc trigger function timing diagram
z32f064 1 product specification uart ps03440 4 - 0417 preliminary 109 12. u art o verview 2 - channel universal asynchronous receiver/ transmitter (uart) modules are included . d edicated dma support to transfer data between the m emory buffer and the t ransmit /r eceive buffer of the uart block is also provided . the uart operation status , including error status , can be read from the status register. the prescaler , which generates proper baud rate, exists for each uart channel. th is prescaler divides the uart clock source which is pclk/2, from 1 to 65535. the baud rate is generated using the clock with a prescaler of 16, and a n 8 - bit precision clock tuning function . programmable interrupt generation function helps control communicatio n via the uart channel . features of the uart include: ? compatible with 16 4 50 uart ? support s dma transfer ? standard asynchronous control bit (start, stop, and parity) configurable ? programmable 16 - bit fractional baud rate generator ? programmable serial communica tion o 5 - , 6 - , 7 - or 8 - bit data transfer o even, odd, or no - parity bit in s ertion and detection o 1 - , 1.5 - or 2 - stop bit - insertion and detection ? 16 - bit b a ud rate generation with 8 - bit fraction control ? hardware inter - frame delay function ? stop bit error detection ? detail status register ? loop - back control
z32f064 1 product specification uart ps03440 4 - 0417 preliminary 110 figure 12 . 1 block d iagram
z32f064 1 product specification uart ps03440 4 - 0417 preliminary 111 pin d escription table 12 . 1 external s ignal pin name type descr iption txd0 o uart channel 0 transmit output rxd0 i uart channel 0 receive input txd1 o uart channel 1 transmit output rxd1 i uart channel 1 receive input r egisters the base a ddress of uart is shown in table 12 . 2 and the regi ster map is described in and table 12 . 3 . table 12 . 2 base a ddress of e ach p ort name base address uart 0 0x4000_8000 uart 1 0x4000_8100 table 12 . 3 uart register m ap n ame o ffset t ype d escription reset value un . rbr 0x00 r receive data buffer register 0x00 un . thr 0x00 w transmit data hold register 0x00 un . ier 0x04 rw interrupt enable register 0x00 un . iir 0x08 r interrupt id register 0x 01 - 0x08 - reserved - un . lcr 0x0c rw line control register 0x00 un . dcr 0x10 rw data control register 0x00 un . lsr 0x14 r line status register 0x00 - 0x18 - reserved - un . scr 0x1c rw scratch pad register 0x00 un . bdr 0x20 rw baud rate divisor latch re gister 0x0000 un . bfr 0x24 rw baud rate fractional counter value 0x00 un . idtr 0x30 rw inter - frame delay time register 0x00
z32f064 1 product specification uart ps03440 4 - 0417 preliminary 112 un . rbr receive buffer register the uart receive buffer register is an 8 - bit read - only register . u0 . rbr=0x4000_8000, u1 . rbr=0x40 00_8100 7 6 5 4 3 2 1 0 rbr[7:0] - ro 7 0 rbr receive buffer register un . thr transmit data hold register the uart transmit data hold register is an 8 - bit write - only register . u0 . thr=0x4000_8000, u1 . thr=0x4000_8100 7 6 5 4 3 2 1 0 thr - wo 7 0 thr transmit data hold register
z32f064 1 product specification uart ps03440 4 - 0417 preliminary 113 un . ier uart interrupt enable register the uart interrupt enable register is an 8 - bit register. u0 . ier=0x4000_8004, u1 . ier=0x4000_8104 7 6 5 4 3 2 1 0 - - dtxien drxien txie rlsie threie drie 0 0 0 0 0 0 0 0 rw rw r w r w r w 5 dtxien dma transmit done interrupt enable 0 receive line status interrupt is disabled 1 receive line status interrupt is enabled 4 drxien dma receive done interrupt enable 0 dma receive done interrupt is disabled 1 dma receive d one interrupt is enabled 3 txie transmit register empty interrupt enable 0 transmit register empty interrupt is disabled 1 transmit register empty interrupt is enabled 2 rlsie receiver line status interrupt enable 0 receive line status interrupt is disabled 1 receive line status interrupt is enabled 1 threie transmit holding register empty interrupt enable 0 transmit holding register empty interrupt is disable d 1 transmit holding register empty interrupt is enable d 0 drie data receive interrupt enable 0 data receive interrupt is disabled 1 data receive interrupt is enabled un . iir uart interrupt id register the uart interrupt id register is an 8 - bit register. u0 . iir=0x4000_8008, u1 . iir=0x4000_8108 7 6 5 4 3 2 1 0 txe iid ip en 0 0 0 0 000 0 r r r 4 txe interrupt source id see interrupt source id table 3 1 iid interrupt source id see interrupt source id table 0 ipen interrupt pending bit 0 interrupt is pending 1 no interrupt is pending.
z32f064 1 product specification uart ps03440 4 - 0417 preliminary 114 the uart supports 3 - priority interrupt generation . the i nterrupt s ource id register shows one interrupt source which has the highest priority among pending interrupts. th is priority is defined in the following order: ? re cei ve line status interrupt ? receive data ready interrupt/ character timeout interrupt ? transmit hold register empty interrupt ? tx/rx dma complete interrup t table 12 . 4 interrupt id and c ontrol priority txe iid ipen interrupt s ources b it4 b it3 b it2 b it1 b it0 interrup t interrupt c ondition interrupt c lear - 0 0 0 0 1 none - - 1 0 0 1 1 0 receiver line status overrun, parity, framing or break error read lsr register 2 0 0 1 0 0 receiver data available receive data is available. read receive register or read iir regist er 3 0 0 0 1 0 transmitter holding register empty transmit buffer empty write transmit hold register or read i ir register 4 1 x x x x transmitter register empty transmit registerr empty write transmit hold register or read iir register 5 0 1 1 0 0 r x dm a done rx dma completed. read iir register 6 0 1 0 1 0 tx dma done tx dma completed. read iir register 7 1 x x x x transmitter register empty and dma done transmitter regiser e m pty and tx dma completed. read iir register
z32f064 1 product specification uart ps03440 4 - 0417 preliminary 115 un . lcr uart line control regist er the uart line control register is an 8 - bit register. u0 . lcr=0x4000_800c, u1 . lcr=0x4000_810c 7 6 5 4 3 2 1 0 break stickp parity pen stopbit dlen 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw 6 break when this bit is set, txd pin will be driven at low st ate in orde r to notice the alert to the receiver. 0 normal transfer mode 1 break transmit mode 5 stickp force parity and it will be effective when pen bit is set. 0 parity stuck is disabled 1 parity stuck is enabled and parity always the bit of pari ty. 4 parity parity mode selection bit and stuck parity select bit 0 odd parity mode 1 even parity mode 3 pen parity bit transfer enable 0 the parity bit disabled 1 the parity bit enabled 2 stopbit the number of stop bit followed by data bits. 0 1 stop bit 1 1.5 / 2 stop bit in case of 5 bit data case, 1.5 stop bit is added. in cas e of 6,7 or 8 bit data, 2 stop bit is added 1 0 dlen the data length in one transfer word. 00 5 bit data 01 6 bit data 10 7 bit data 1 1 8 bit data parity bit is generated according to bit 3, 4, 5 of unlcr register. the following table shows the variation of parity bit generation. stickp parity pen parity x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity as
z32f064 1 product specification uart ps03440 4 - 0417 preliminary 116 un . dcr uart data control register the uart data control register is an 8 - bit register. u0 . dcr=0x4000_8010, u1 . dcr=0x4000_8110 7 6 5 4 3 2 1 0 lbon rxinv txinv 0 0 0 0 0 0 0 0 rw rw 4 lbon local loopback test mode enable 0 normal mode 1 local loopback mode (txd connected to rxd internally) 3 rxinv rx data inversion selection 0 normal rxdata input 1 inverted rxdata input 2 txinv tx data inversion selection 0 normal txdata output 1 inverted tx data output
z32f064 1 product specification uart ps03440 4 - 0417 preliminary 117 un . lsr uart line status register the uart line status register is an 8 - bit register. u0 . lsr=0x4000_8014, u1 . lsr=0x4000_8114 7 6 5 4 3 2 1 0 - temt thre bi fe pe oe dr 0 1 1 0 0 0 0 0 r r r r r r r 6 temt transmit empty. 0 transmit register has the data is now transferring 1 transmit register is empty. 5 thre transmit holding empty. 0 transmit holding register is not empty. 1 transmit holding register empty 4 bi break condition indication bit 0 normal status 1 brea k condition is detected 3 fe frame error. 0 no framing error. 1 framing error. no valid stop bit in receive charact ert 2 pe parity error 0 no parity error 1 parity error. the receive character does not have correct parity information. 1 oe o verrun error 0 no overrun error 1 overrun error. additional data arrives when the r hr is full 0 dr data received 0 no data in receive holding register. 1 data received and saved in receive holding registe r this register provides the s t atus o f data transfers between the transmitter and receiver. user s can get the line status information from this register and handle the next process. bits 1,2,3, a nd 4 will cause the line status interrupt when rlsie bit in unien register is set. other bits gene rate an interrupt when their interrupt enable bit in unien register is set.
z32f064 1 product specification uart ps03440 4 - 0417 preliminary 118 un . bdr baud r ate divi sor latch register the uart baud r ate divisor latch register is a 16 - bit register. u0 . bdr=0x4000_8020, u1 . bdr=0x4000_8120 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bdr 0x0000 rw 15 0 bdr baud rate divider latch value to establish communication with the uart chann el, the baud rate should be set . the baud rate for the baud rate generator is determined using divider values from 1 to 65535 the 16 bit divider re gister ( unbdr ) is written for desired baud rate. the b aud rate calculation formula is shown below. bdr = ??? ? ???? 32 ???????? for a speed of 48 mhz uart_pclk , the divider value and error rate is described in table table 12 . 5 . table 12 . 5 example of b aud r ate c alculation (without bfr) uart_pclk= 48 mhz baud r ate divider error ( %) 1200 1250 0.00% 2400 625 0.0 0 % 4800 312 0.16% 9600 156 0.16% 19200 78 0.16% 38400 39 0 . 16 % 57600 26 0.16% 115200 13 0 . 16 %
z32f064 1 product specification uart ps03440 4 - 0417 preliminary 119 un . bfr baud r ate fr action counter register the baud r ate fraction c ounter r egister is an 8 - bit register. u0 . bfr=0x4000_8024, u1 . bfr=0x4000_8124 7 6 5 4 3 2 1 0 bfr 0x00 rw 7 0 bfr fractions counter value. 0 fraction counter is disabled n fraction counter enabled. fraction compensation m ode is operating. fraction counter is incremented by fcnt. table 12 . 6 example of b aud r ate c alculation uart_pclk= 48 mh z baud r ate divider fcnt error ( %) 1200 1250 0 0.0% 2400 625 0 0.0% 4800 312 128 0.0% 9600 156 64 0.0% 19200 78 32 0.0% 38400 39 16 0.0% 57600 26 10 0.0 1 % 115200 13 5 0.0 1 % bfr = float ? 256 the fcnt value can be calculated using the equation above. for example, if the target baud rate is 4800 bps and uart_pclk is 48 mhz, the bdr value is 312.5. using the integer 312 as the bdr value and the floating number 0.5, the fnct value will be 128, as shown in the following calculation: fcnt = 0.5 * 256 = 128 the 8 - bit fractional counter will count up by the bfr value every (baud rate)/16 periods and whenever the fractional counter overflows, the divisor value will increment by 1. theref ore, this period will be compensated. in the next period, the divisor value will return to the original set value.
z32f064 1 product specification uart ps03440 4 - 0417 preliminary 120 un . idtr inter - frame delay time register the uart inter - frame time register is an 8 - bit register. a d ummy delay can be inserted between tw o continuous transmits. u0 . idtr=0x4000_8030, u1 . idtr=0x4000_8130 7 6 5 4 3 2 1 0 - waitval 0 0 0 0 0 000 rw 2 0 waitval wait time is decided by this value ???? ???? = ??????? ????????
z32f064 1 product specification uart ps03440 4 - 0417 preliminary 121 functional description gener al operation the uart module is compatible with 16450 uart. additionally , dedicated dma channels and fractional baud rate compensation logic are provided. this uart module does not have an internal fifo block. therefore, data transfers are establish ed eith er interactively or with dma support. the dma operation is described in this section. two dma channels are provided for each uart module C one channel is for tx transfer and the other one is for rx transfer. each channel has a 32 - bit memory address registe r and a 16 - bit transfer counter register. prior to dma operation, the dma m emory a ddress r egister and the t ransfer c ount r egister should be configured. for the rx operation, the memory address is the destination memory address and for the tx operation, the memory address is the source memory address. the transfer counter register store s the number count of transfer data. each time a single transfer is done, the counter is decremented by 1. when the cou n ter reaches zero, the dma done flag is delivered to the uart control block. if the interrupt is enabled, this flag generate s the interrupt. receiver sampling timing the uarts operates with the following timing . if the falling edge is on the receive line, the uart determines it to be the start bit. from the sta rt timing, uart oversamples 16 times of 1 - bit and detect s the bit value at the 7th sample of 16 samples . figure 12 . 2 . sampling timing of uart receive r note: e nable the debounce settings in the pc u block to reinforce the immunity of external glitch noise. u n rxd subsample 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 u n rxd bit samples start bit 0 1 0 0 0 0 1 0 stop bit start bit 0 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 stop bit bit sampling position (7/16)
z32f064 1 product specification uart ps03440 4 - 0417 preliminary 122 t ransmitter the transmitters function is to transmit data t ransmit . the start bit, data bits, optional parity bit , and stop bit are serially shifted, with the least significant bit first. the number of dat a bit s is selected in the dlan[1:0] field in the un.lcr register. the parity bit is set according to the parity and pen bit fi e l d in the un.lcr register. if the parity type is even , the parity bit depends on the one bit sum of all data bits. for odd parity , the parity bit is the inverted sum of all data bits. the number of stop bits is selected in the stopbit field in the un.lcr register. an example of transmit data format is shown figure 12 . 3 . transmit data format example inter - frame delay transmission the inter - frame delay function allows the transmitter to insert an id le state on the txd line between two characters. the width of the id le state is defined in the waitval field of the un.idtr register. when this field is set to 0, zero time - delay is generated. otherwise, the transmitter holds a high level on txd after each transmitted character during the number of bit periods defined in the watival field. figure 12 . 4 . inter - frame delay timing diagram transmit interrupt the transmit operation generates interrupt flags. when the transmitter holding register is empty, the thre interrupt flag will be set. whe n the transmitter shifter register is empty, the txe i nterrupt flag will be set. users can select the interrupt timing that is best for the application.
z32f064 1 product specification uart ps03440 4 - 0417 preliminary 123 figure 12 . 5 . transmit inte rrupt timing diagram dma transfers the uart support s the dma interface function. i t is provided as an option, depending on the device. the start memory address for transfer data and the length of transfer data are programm e d in the registers in the dma bl ock. the end of transfer is notified via the related transfer done flag. the t ransmit with dma operation invoke s the dma tx done flag dtx.uniir and set s the dma tx done interrupt id when all the transmit data are written to the transmit holding register. tw o transmit data are remain in registers in the uart block after the dma transfer done interrupt. the r eceive with dma operation i nvoke s the rxt.uniir dma rx done flag and set s the dma rx done interrupt id when all the receive data are written to the destin ation memory. therefore , the uart rxd signal is already in idle state when the dma rx done interrupt is issued.
z32f064 1 product specification serial peripheral interface ps03440 4 - 0417 preliminary 124 13. s erial p eripheral i nterface o verview one - c hannel serial interface is provided for synchronous serial communications with external peripherals . the s erial p eripheral i nterface (spi) block support s both master and slave mode s . four signals are used for spi communication C ss, sck, mosi, and miso. ? master or slave operation. ? programmable clock polarity and phase. ? 8, 9, 16, 17 - bit wide transmit/rece ive register. ? 8, 9, 16, 17 - bit wide data frame. ? loop - back mode. ? programmable start, burst, and stop delay time. ? dma transfer operation. figure 13 . 1 sp i b lock d iagram
z32f064 1 product specification serial peripheral interface ps03440 4 - 0417 preliminary 125 p in d escription table 13 . 1 external pins pin name type d escription ss0 i/o spi0 slave select input / output sck0 i/o spi0 serial clock input / output mosi0 i/o spi0 serial data ( master output, slave input ) miso0 i/o spi0 serial data ( master input, slave output ) r egisters the base address of spi is 0x4000_9000 and the registe r map is described in table 13 . 3 . table 13 . 2 spi base address n ame base a ddress spi 0 0x4000_9 0 00 table 13 . 3 spi register map name offset type description reset value sp 0 . tdr 0x00 w spi 0 transmit data register - sp 0 . rdr 0x00 r spi 0 receive data register 0x000000 sp 0 . cr 0x04 rw spi 0 control registe r 0x001020 sp 0 . sr 0x08 rw spi 0 status register 0x00000 6 sp 0 . br 0x0c rw spi 0 baud rate register 0x0000ff sp 0 . en 0x10 rw spi 0 enable register 0x000000 sp 0 . lr 0x14 rw spi 0 delay length register 0x010101 sp 0 . tdr spi transmit data register sp 0. tdr is a 1 7 - bit read/write register. it contains serial transmit data. sp0.tdr=0x4000_9000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tdr 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000 rw 16 0 tdr transmit data register
z32f064 1 product specification serial peripheral interface ps03440 4 - 0417 preliminary 126 sp 0 . rdr spi receive data register sp 0. rdr is a 17 - bit read/write register. it contains serial receive data. sp0.rdr=0x4000_9000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rdr 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000 rw 16 0 rdr receive data register sp 0 . cr spi control register sp 0. cr is a 20 - bit read/write register which can be set to configure spi operati on mode. sp0.cr=0x4000_9004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 txbc rxbc tx d ie rx d ie sscie txie rxie ssmod ssout lbe ssma s k ssmo sspol ms msbf cpha cpol bitsz 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 00 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 20 txbc tx buffer clear bit. 0 no action 1 clear tx buffer 19 rxbc rx buffer clear bit 0 no action 1 clear rx buffer 18 txdie dma tx done interrupt enable bit. 0 dma tx done interrupt is disabled. 1 dma tx done interrupt is enabled. 17 rxdie dma rx done interrupt enable bit. 0 dma rx done interrupt is disabled. 1 dma rx done interrupt is enabled. 16 sscie ss edge change interrupt enable bit. 0 nss interrupt is disabled. 1 nss interrupt is enabled for both edges (l ? h, h ? l) 15 txie transmit interrupt enable bit. 0 transmit interrupt is disabled. 1 transmit interrupt is enabled. 14 rxie receive interrupt enable bit.. 0 receive interrupt is disable d. 1 receive interrupt is enabled. 13 ssmod ss auto/manual output select bit.
z32f064 1 product specification serial peripheral interface ps03440 4 - 0417 preliminary 127 0 ss output is not set by ssout (spncr[12]). - ss signal is in normal operation mode. 1 ss output signal is set by ssout. 12 ssout ss output signal select bit. 0 ss output is l. 1 ss output is h. 11 lbe loop - back mode select bit in master mode. 0 loop - back mode is disabled. 1 loop - back mode is enabled. 10 ssmask ss signal masking bit in slave mode. 0 ss signal masking is disabled. - receive data when ss signal is active. 1 ss signal masking is enabled. - receive data at sclk edges. ss signal is ignored. 9 ssmo ss output signal select bit. 0 ss output signal is disabled. 1 ss output signal is enabled. 8 sspol ss signal polarity select bit. 0 ss signal is active - low. 1 ss signal is active - high. 7 6 reserved 5 ms master/slave select bit. 0 spi is in slave mode. 1 spi is in master mode. 4 msbf msb/lsb transmit select bit. 0 lsb is transferred first. 1 msb is transferred first . 3 cpha spi clock phase bit. 0 sampling of data occurs at odd edges (1,3,5,,15). 1 sampling of data occurs at even edges (2,4,6,,16). 2 cpol spi clock polarity bit. 0 active - high clocks selected. 1 active - low clocks selected. 1 0 bitsz transmit/receive data bits select bit. 00 8 bits 01 9 bits 10 16 bits 11 17 bits cpol=0, cpha=0 : data sampling at rising edge, data changing at falling edge cpol=0, cpha=1 : data sampling at falling edge, data changing at rising edge cpol=1, cpha=0 : data sampling at falling edge, data changing at rising edge cpol=1, cpha=1 : data sampling at rising edge, data changing at falling edge
z32f064 1 product specification serial peripheral interface ps03440 4 - 0417 preliminary 128 sp 0 . sr spi status register sp 0. sr is a 10 - bit read/write register. it contains the status of the spi . sp0 . sr=0x4000_900 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 txdmaf rxdmaf ssdet sson ovrf udrf txidle trdy rrdy 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 rc1 rc1 rc1 rc1 rc1 rc1 r r r 9 txdmaf dma transmit operation complete flag. (dma to spi) 0 dma transmit op is working or is disabled. 1 dma transmit op is done. 8 rxdmaf dma receive operation complete flag. (spi to dma ) 0 dma receive operation is working or is disabled. 1 dma transmit op is done. 7 reserved 6 ssdet the rising or falling edge of ss signal detect flag. 0 ss edge is not detected. 1 ss edge is detected. - the bit is cleared when it is written as 0. 5 sson ss signal status flag. 0 ss signal is inactive. 1 ss signal is active. 4 ovrf receive overrun e rror flag. 0 receive overrun error is not detected. 1 receive overrun error is detected. - this bit is cleared by writing or reading spnrdr. 3 udrf transmit underrun error flag. 0 transmit underrun is not occurred. 1 transmit underrun is occurr ed. - this bit is cleared by writing or reading spntdr. 2 txidle transmit/receive operation flag. 0 spi is transmitting data 1 spi is in idle state. 1 trdy transmit buffer empty flag. 0 transmit buffer is busy. 1 transmit buffer is ready. - t his bit is cleared by writing data to spntdr. 0 rrdy receive buffer ready flag. 0 receive buffer has no data. 1 receive buffer has data. - this bit is cleared by writing data to spnrdr.
z32f064 1 product specification serial peripheral interface ps03440 4 - 0417 preliminary 129 sp 0 . br spi baud rate register sp 0. br is a 16 - bit read/write register. baud rate is set by writing the register. sp0 . b r=0x4000_900 c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 br 0x00ff rw 15 0 br baud rate setting bits baud rate = pclk / (br + 1) (br must be bigger than 0, br >= 2 ) sp 0 . en spi e n able r egister sp 0. en is a bit read/write register. it contains the spi enable bit. sp0.en=0x4000_9010 7 6 5 4 3 2 1 0 enable 0 0 0 0 0 0 0 0 rw 0 enable spi enable bit 0 spi is disabled. - spnsr is initialized by writing 0 to this bit but other regi sters ar ent initialized. 1 spi is enabled. - when this bit is written as 1, the dummy data of transmit buffer will be shifted. to prevent this, write data to sptdr before this b it is active. note: when in spi slave mode, ensure that you disable the sp i prior to loading the tdr register, then enable it to prevent an extra byte from being sent.
z32f064 1 product specification serial peripheral interface ps03440 4 - 0417 preliminary 130 sp 0 . lr spi d elay length register sp 0. lr is a 24 - bit read/write register. it contains start, burst, and stop length value. sp0.lr=0x4000_9014 31 30 29 28 27 2 6 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spl btl stl 0 0 0 0 0 0 0 0 0x01 0x01 0x01 rw rw rw 23 16 spl stoplength value 0x01 ~ 0xff : 1 ~ 255 sclks. (spl 1) 15 8 btl burstlength value 0x01 ~ 0xff : 1 ~ 255 sclks. (btl 1) 7 0 stl start length value 0x01 ~ 0xff : 1 ~ 255 sclks. (stl 1) figure 13 . 2 sp i w ave f orm (stl, btl and spl)
z32f064 1 product specification serial peripheral interface ps03440 4 - 0417 preliminary 131 functio nal description the spi transmit block and receive block share the clock gen block ; however, they are independent of each other. the transmit and receive block s contain double buffers and spi is available for back to back transfer operation. spi t iming the spi has four modes of operation. these modes essentially control the way data is clocked in or out of an spi device. the configuration is done by two bits in the spi control register (spncr). the clock polarity is specified by the cpol control bit, which selects an active high or active low clock. the clock phase (cpha) control bit selects one of the two fundamentally differe nt transfer formats. to ensure proper communication between master and slave , both devices must run in the same mode. this may requir e a reconfiguration of the master to match the requirements of different peripheral slaves. the clock polarity has no significant effect on the transfer format. switching this bit causes the clock signal to be inverted (active high becomes active low and i dle low becomes idle high). the settings of the clock phase, however, select one of the two different transfer timings, which are described in detail in the following two chapters. because the mosi and miso lines of the master and the slave are directly co nnected to each other, the diagrams show the timing of both device s. the n ss line is the slave select input of the slave. the n ss pin of the master is not shown in the diagrams. it has to be inactive by a high level on this pin (if configured as input pin) or by configuring it as an output pin. the timing of a spi transfer where cpha is zero is shown in figure 13 . 3 and figure 13 . 4 . two wave forms are shown for the sck sign al : one for cpol equals zero a nd another for cpol equals one. when the spi is configured as a slave, the transmission starts with the falling edge of the /ss line. this activates the spi of the slave and the msb of the byte stored in its data register (spntd r) is output on the miso line. the actual transfer is started by a software write to the spntdr of the master. this causes the clock signal to be generated. in cases where the cpha equals zero, the sclk signal remains zero for the first half of the first s clk cycle. this ensures that the data is stable on the input lines of both the master and the slave. the data on the input lines is read with the edge of the sclk line from its inactive to its active. the edge of the sclk line from its active to its inacti ve state (falling edge if cpol equals zero and rising edge if cpol equals one) causes the data to be shifted one bit further so that the next bit is output on the mosi and miso lines. figure 13 . 3 transfer ti ming 1/ 4 ( cpha=0, cpol=0, msbf=0) sck mosi miso d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7
z32f064 1 product specification serial peripheral interface ps03440 4 - 0417 preliminary 132 figure 13 . 4 spi transfer timing 2/ 4 ( cpha=0, cpol=1, msbf=1) the timing of a spi transfer where cpha is one is shown in figure 13 . 5 and figure 13 . 6 . two wave forms are shown for the sclk signal - one for cpol equals zero and another for cpol equals one. similar to the previous cases , the falling edge of the n ss lines selects and activates the slave. compared to the previo us cases, where cpha equals zero, the transmission is not started and the msb is not output by the slave at this stage. the actual transfer is started by a software write to the spntdr of the master wh ich causes the clock signal to be generated. the first edge of the sclk signal from its inactive to its active state (rising edge if cpol equals zero and falling edge if cpol equals one) causes both the master and the slave to output the msb of the byte in the spntdr. as shown in figure 13 . 3 and figure 13 . 4 , there is no delay of half a sclk - cycle. the sclk line changes its level immediately at the beginning of the first sclk - cycle. the data on the input lines is read with the edge of the sclk line from its active to its inactive state (falling edge if cpol equals zero and rising edge if cpol equals one). after eight clock pulses , the transmission is completed. ss sck mosi miso d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0
z32f064 1 product specification serial peripheral interface ps03440 4 - 0417 preliminary 133 figure 13 . 5 spi transfer timing 3 / 4 ( cpha=1, cpol=0, msbf=0) figure 13 . 6 spi transfer t iming 4/ 4 ( cpha=1, cpol=1, msbf=1) ss sck ss mosi miso d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 ss sck mosi miso d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0
z32f064 1 product specification serial peripheral interface ps03440 4 - 0417 preliminary 134 dma handshake spi supports the dma handshaking operation. in order to operate a dma handshake, dma registers should first be set . (refer to chapter 6, d irect m emory a ccess c ontroller ). as the t ransmitter and r eceiver are independent of each other, spi can operate the two channels at the same time. after the dma channel for the receiver is enab led and the receive buffer is filled, spi sends an rx request to the dma to empty the buffer and waits for an ack signal from dma. if the receive buffer is filled again after the ack signal, spi sends an rx request. if dma rx done becomes high, rx dma f ( spn sr[8]) becomes 1 and an interrupt is serviced when rxd ie ( spncr[17]) is set. similarly , if the transmit buffer is empty after the dma channel for the transmitter is enabled, spi sends a tx request to the dma to fill the buffer and waits for an ack signal f rom dma. if the transmit buffer is empty again after the ack signal, spi sends a tx request. if dma tx done becomes high, tx dma f (spnsr[9]) becomes 1 and an interrupt is serviced when tx die(spncr[1 8 ]) is set. the s lave transmitter sends dummy data at the fi rst transfer (8~1 7 sclks) in dma handshake mode. figure 13 . 7 dma handshake flow c hart
z32f064 1 product specification i2c interface ps03440 4 - 0417 preliminary 135 14. i 2 c interface o verview inter - integrated circuit (i 2 c ) bus serves as an interface between the microcontroller and the s erial i 2 c bus. i t provides two wires , serial bus interface to a large number of popular devices and allows parallel - bus systems to communicate bidirectionally with the i 2 c - bus. ? master and slave operation ? programmable communication speed ? multi - master bus co nfiguration ? 7 - bit addressing mode ? standard data rate of 100/400 kbps ? stop signal generation and detection ? start signal generation ? ack bit generation and detection figure 14 . 1 i 2 c block d iagram sda f/f 8 - bit shift register ( shftr) slave addr. register1 (i2csar1) noise canceller (debounce ) data out register (i2cdr) scl high period register (i2csclhr) scl low period register (i2cscllr) sdaholdtimeregister (i2cdahr) sda out controller scl out controller s c l noise can celler (debounce ) i n t e r n a l b u s l i n e sdain sdaou t scli n sclou t 1 0 1 0 d ebounce enable d ebounce enable
z32f064 1 product specification i2c interface ps03440 4 - 0417 preliminary 136 pin descrip tion table 14 . 1 i 2 c i nterface e xternal p ins pin name t ype d escription scl0 i/o i 2 c channel 0 serial clock bus line (open - drain) sda0 i/o i 2 c channel 0 serial data bus line (open - drain) r egisters the base ad dress of i 2 c 0 is 0x4000_a000 . the register map is described in table 14 . 3 . table 14 . 2 i 2 c i nterface b ase a ddress n ame base address i 2 c 0 0x4000_a 0 00 table 14 . 3 i 2 c r egister m ap n ame offset type description reset value ic n . d r 0x00 rw i 2 c 0 data register 0xff ic n . sr 0 x 08 r, rw i 2 c 0 status register 0x00 ic n . s ar 0 x 0c rw i 2 c 0 slave address register 0x00 ic n . cr 0x14 rw i 2 c 0 control registe r 0x00 ic n . scll 0x18 rw i 2 c 0 scl low duration register 0x ff ff ic n . sclh 0 x 1c rw i 2 c 0 scl high duration register 0x ff ff ic n . sdh 0x20 rw i 2 c 0 sda hold register 0x7f
z32f064 1 product specification i2c interface ps03440 4 - 0417 preliminary 137 icn . dr i 2 c data register icn . dr is an 8 - bit read/write register. it contains a byte of s erial data to be transmitted or a byte which has just been received. ic0.dr=0x4000_a000 7 6 5 4 3 2 1 0 dr 0xff rw 7 0 dr the most recently received data or data to be transmitted. icn . sr i 2 c status register icn . s r is an 8 - bit read/write register. it contains the status of i 2 c bus interface. writing to the register clears the status bits except for imaster. ic0 . sr=0x4000_ a008 7 6 5 4 3 2 1 0 gcall tend stop ssel mlost busy tmod e rxack 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw 7 gcall general call flag 0 general call is not detected. 1 general call detected or slave address (id byte) was sent. 6 tend 1 byte transmission complete flag 0 the transmission is working or not completed. 1 the transmission is completed. 5 stop stop flag 0 stop is not detected. 1 stop is detected. 4 ssel slave flag 0 slave is not selected. 1 slave is selected. 3 mlost mastership lost flag 0 mastership is not lost. 1 mastership is lost. 2 busy busy flag 0 i 2 c bus is in idle state. 1 i 2 c bus is busy. 1 tmode transmitter/receiver mode flag 0 receiver mode. 1 transmitter mode. 0 rxack rx ack flag 0 rx ack is not received. 1 rx ack is received.
z32f064 1 product specification i2c interface ps03440 4 - 0417 preliminary 138 icn . sar i 2 c slave address register icn . sar is an 8 - bit read/write register. it shows the address in s lave m ode. ic0.sar=0x4000_a00c 7 6 5 4 3 2 1 0 svad gcen 0x00 0 rw rw 7 1 svad 7 - bit slave address 0 gcen general call enable bit 0 general call is disabled. 1 general call is enabled. icn . cr i 2 c control register icn . cr is an 8 - bits read/write register. the register can be set to configure i2c operation mode and simultaneously allowed for i2c transactions to be kicked off. ic0.cr=0x4000_a014 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 intdel iif softrst inten acken s top start 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 rw r rw rw rw rw rw 9 8 intdel interval delay value between address and data transfer (or data and data) 0 1 * icnscll 1 2 * icnscll 2 4 * icnscll 3 8 * icnscll 7 iif interrupt status bit 0 i nterrupt is inactive 1 interrupt is active 5 softrst soft reset enable bit. 0 soft reset is disabled. 1 soft reset is enabled.. 4 inten interrupt enabled bit. 0 interrupt is disabled. 1 interrupt is enabled. 3 acken ack enable bit i n receiver mode. 0 ack is not sent after receiving data. 1 ack is sent after receiving data. 1 stop stop enable bit. when this bit is set as 1 in transmitter mode, next transmission will be stopped even though ack signal has been received. 0 st op is disabled.
z32f064 1 product specification i2c interface ps03440 4 - 0417 preliminary 139 1 stop is enabled. when this bit is set, transmission will be stopped. 0 start transmission start bit in master mode. 0 waits in slave mode. 1 starts transmission in master mode. figure 14 . 2 intdel in master m ode icn . scll i 2 c s cl low d uration register icnscll is a 16 - bit read/write register. scl low time can be set by writing this register in m aster m ode. ic0 . sdll=0x4000_a018 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scll 0xffff r w 15 0 scll scl low duration value. scll = ( pclk * scll[15:0] ) + 2 * pclks default value is 0xffff. figure 14 . 3 scl low timing
z32f064 1 product specification i2c interface ps03440 4 - 0417 preliminary 140 icn . sclh i 2 c scl high d uration register icnsclh is a 16 - bit read/write re gister. scl high time will be set by writing this register in m aster m ode. ic0 . sdlh=0x4000_a01c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sclh 0xffff rw 15 0 sclh scl high duration value. sclh = ( pclk * sclh[15:0] ) + 3 pclks default value is 0xffff. figure 14 . 4 scl low timing icn . sdh sda hold register icnsdh is a 15 - bit read/write register. sda hold time is set by writing this register in m aster m ode. ic0 . sdh=0x4000_a020 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdh 0x3fff rw 14 0 sdh sda hold time setting value. sdh = ( pclk * sdh[14:0] ) + 4 pclks default value is 0x3fff.
z32f064 1 product specification i2c interface ps03440 4 - 0417 preliminary 141 figure 14 . 5 sda hold timin g
z32f064 1 product specification i2c interface ps03440 4 - 0417 preliminary 142 f unctional d escription i 2 c b it t ransfer t he data on the sda line must be stable during the h period of the clock. the h or l state of the data line can only change when the clock signal on the scl line is l ; see figure 14 . 6 . figure 14 . 6 i 2 c bus bit t ransfer scl sda
z32f064 1 product specification i2c interface ps03440 4 - 0417 preliminary 143 start / repeated start /s top within the procedure of the i 2 c - bus, unique situations arise which are defined as s tart(s) and stop(p) conditions ; see figur e 14 . 7 . an h to l transition on the sda line while scl is h is one such unique case. this situation indicates a start condition. a n l to h transition on the sda line while scl is h defines a stop condition. start and stop conditions are always generated by the master. the bus is considered to be busy after the start condition. the bus is considered to be free again a certain time after the stop condition. the bus is busy if a repeated start(sr) is generated instead of a stop condition. in this respect, the start(s) and repeated start(sr) conditions are functionally identical. for the remainder of this document therefore, the s symbol will be used as a generic term to represent both the start and repeated start conditions, unless sr is particularly relevant. detection of start an d stop conditions by devices connected to the bus is easy if they incorporate the necessary interfacing hardware. however, microcontrollers with no such interface have to sample the sda line at least twice per clock period to sense the transition. figur e 14 . 7 start and stop c onditi on scl sda start condition s p stop condition
z32f064 1 product specification i2c interface ps03440 4 - 0417 preliminary 144 data transfer every byte put on the sda line must be 8 - bits long. the number of bytes that can be transmitted per transfer is unrestricted. each byte must be followed by an acknowledge bit. data is transferred with the most significant bit (msb) first ; see figure 14 . 8 . if a slave can t receive or transmit another complete byte of data until it has performed some other function, for example servicing an internal interrupt, it can hold the clock line scl l to force the master into a wait state. data transfer then continues when the slave is ready for another byte of data and releases clock line scl. a message which starts with such an address can be t erminated by generation of a stop condition, even during the transmission of a byte. in this case, no acknowledge ment is generated. figure 14 . 8 i 2 c bus d ata t ransfer start or repeated start condition s or sr stop or rep eated start condition sr or p msb acknowledgemen t signal f r om slave acknowledgement signal f r om slave byte complete, interrupt within device clock line held low while interrupts are served. 1 9 1 9 ack ack sda scl sr p
z32f064 1 product specification i2c interface ps03440 4 - 0417 preliminary 145 acknowledge data transfer with acknowl edge ment is obligatory. the acknowledge - related clock pulse is generated by the master. the transmitter releases the sda line (high) during the acknowledge clock pulse. the receiver must pull down the sda line during the acknowledge clock pulse so that it remains stable l during the h period of this clock pulse ; see figure 14 . 9 . s et - up and hold times must also be taken into account. when a slave doesn t acknowledge the slave address (for example, it s unable to receive or trans mit because it s performing some real - time function), the data line must be left h by the slave. the master can then generate either a stop condition to abort the transfer, or a repeated start condition to start a new transfer. if a slave - receiver acknow ledge s the slave address but cannot receive any more data bytes later during the transfer , the master must again abort the transfer. this is indicated by the slave generating the not - acknowledge on the first byte to follow. the slave leaves the data line h and the master generates a stop or a repeated start condition. if a master - receiver is involved in a transfer, it must signal the end of data to the slave - transmitter by not generating acknowledge on the last byte that was clocked out of the slave. the slave - transmitter must release the data line to allow the master to generate a stop or repeated start condition. figure 14 . 9 i 2 c b us a cknowledge ment 1 2 8 data outpu t by transmitter 9 ac k nac k clock pulse for ack data output by receiver scl from master
z32f064 1 product specification i2c interface ps03440 4 - 0417 preliminary 146 high counter reset fast device sclout slow device sclout scl w ait high counting start high counting synchronization all masters generate their own clock on the scl line to transfer messages on the i 2 c - bus. data is only valid during the h period of the clock. a defined clock is therefore needed for the bit - by - bit arbitration procedure to take place. clock synchronization is performed using the wired - and con nection of i 2 c interfaces to the scl line. this means that a n h to l transition on the scl line will cause the devices concerned to start counting off their l period and, once a device clock has gone l , it will hold the scl line in that state until the clock h state is reached ; see figure 14 . 10 . however, the l to h transition of this clock may not change the state of the scl line if another clock is still within its l by the device with the longest l period. devic es with shorter l periods enter a n h wait - state during this time. when all devices concerned have counted off their l period, the clock line will be released and go h . there will then be no difference between the device clocks and the state of the scl line, and the devices will start counting their h periods. the first device to complete its h period will again pull the scl line l . figure 14 . 10 clock s ynchronization d uring the arbitration p roce dure
z32f064 1 product specification i2c interface ps03440 4 - 0417 preliminary 147 arbitration a master may start a transfer only if the bus is free. two or more masters may generate a start condition within the minimum hold time of the start condition which results in a defined start condition to the bus. arbitration takes place on the sda line, while the scl line is at the h level, in such a way that the master which transmits h level, while another master is transmitting l level will switch off its data output stage because the level on the bus doesn t correspond to its ow n level. arbitration can continue for many bits. its first stage is comparison of the address bits. if the masters are each trying to address the same device, arbitration continues with comparison of the data - bits if they are master - transmitter or acknowle dge - bits if they are master - receiver. because address and data information on the i 2 c - bus is determined by the winning master, no information is lost during the arbitration process. a master that loses the arbitration can generate clock pulses until the en d of the byte in which it loses the arbitration. if a master also incorporates a slave function and it loses arbitration during the addressing stage, it s possible that the winning master is trying to address it. the losing master must therefore switch ove r immediately to its slave mode. figure 14 . 11 shows the arbitration procedure for two masters. of course, more may be involved (depending on how many masters are connected to the bus). as soon as there is a difference between the internal data level of the master generating device1 dataout and the actual level on the sda line, its data output is switched off, which means that a h output level is then connected to the bus. this will not affect the data transfer initiated by the wi nning master. figure 14 . 11 arbitration p rocedure b etween two m asters device1 dataout scl on bus device2 dataout sda on bus s arbitration process not adapted device 1 loses arbitration device1 outputs high
z32f064 1 product specification i2c interface ps03440 4 - 0417 preliminary 148 i 2 c operation i 2 c supports the interrupt operation. after interrupt is serviced, iif(icnsr[10 ] ) flag is set. icnsr shows i 2 c - bus status information and scl line stays l before the register is written as a certain value. t he status register can be cleared by writing a zero. master transmitter the master transmitter sh ows the flow of the transmitter in m aster m ode (see figure 14 . 12 ). figure 14 . 12 transmitter flowchart in master m ode from master to slave / master command or data write from slave to master ack interrupt , scl line is held low interrupt after stop command p arbitration l ost as master and addressed as slave lost & other master continues master receiver sla+w ack data rs stop lost lost& stop lost s or sr sla+r y n ack stop y n lost? y cont? y n stop lost p p p
z32f064 1 product specification i2c interface ps03440 4 - 0417 preliminary 149 master receiver the master receiver shows the flow of the receiver in m aster m ode (see figu re 14 . 13 ). figu re 14 . 13 receiver flowchart in master m ode from master to slave / master command or data write slave addr. register (i2csar) from slave to master ack interrupt , scl line is held low interrupt after stop command p ack arbitration lost as master and addressed as slave lost & other master continues master transmitter sla+r ack data rs lost lost& stop lost s or sr data line stable: data valid exept s, sr, p chang e of data allowed sla+w y n ack stop y n lost p p sr idleidle
z32f064 1 product specification i2c interface ps03440 4 - 0417 preliminary 150 slave transmitter the slave transmitter shows the flow of the transmitter in s lave m ode (see figure 14 . 14 ). figure 14 . 14 transmitter flowchart in slave m ode sla+r ack data lost& s or sr y ack stop y n p idle idle y gcall from master to slave / master command or data write from slave to master ack interrupt , scl line is held low interrupt after stop command p arbitration lost as master and addressed as slave lost& general call address gcall
z32f064 1 product specification i2c interface ps03440 4 - 0417 preliminary 151 slave receiver the slave receiver shows the flow of the receiver in s lave m ode (see figure 14 . 15 ). figure 14 . 15 receiver flowchart in slave m ode sla+w ack data lost& s or sr y n ack stop y n p idle idle y gcall from master to slave / master command or data write from slave to master ack inter rupt , scl line is held low interrupt after stop command p arbitration lost as master and addressed as slave lost& general call address gcall
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 152 15. m otor p ulse w idth m odulator introduction the motor pulse width modulator ( mpwm ) is a 16 - bit programmable motor controller with the following features: ? 6 - c h annel outputs for motor control ? 16 - bit counter ? d ead - time support s ? protection event and over voltage event handling ? 6 adc trigger output s ? interval interrupt mode ? u p - down count mode figure 15 . 1 block diagram
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 153 pin d escription table 15 . 1 external signal s pin name t ype d escription m p0 u h o m pwm 0 phase - u h - side output m p0 ul o m pwm 0 phase - u l - side output m p0 v h o m pwm 0 phase - v h - side output m p0 v l o m pwm 0 phase - v l - side output m p0 wh o m pwm 0 phase - w h - side ou tput m p0 w l o m pwm 0 phase - w l - side output prtin 0 i m pwm 0 protection input ovin 0 i m pwm 0 over - voltage input r egisters the base address of mpwm is 0x4000_4000 . table 15 . 2 shows the r egister memory map. table 15 . 2 mpwm register m ap name o ffset t ype d escription reset value mp 0 . mr 0x0000 rw m pwm mode register 0x00 00_0000 mp 0 . olr 0x0004 rw m pwm output level register 0x00 00_0000 mp 0 . fo l r 0x0008 rw m pwm force output re gister 0x00 00_0000 mp 0 . prd 0x000c rw m pwm period register 0x 0000_00 02 mp 0 . d uh 0x0010 rw m pwm duty uh register 0x 0000_00 01 mp 0 . d vh 0x0014 rw m pwm duty vh register 0x 0000_00 01 mp 0 . d w h 0x0018 rw m pwm duty wh register 0x 0000_00 01 mp 0 . d u l 0x001c rw m pwm du ty ul register 0x 0000_00 01 mp 0 . d v l 0x0020 rw m pwm duty vl register 0x 0000_00 01 mp 0 . d w l 0x0024 rw m pwm duty wl register 0x 0000_00 01 mp 0 . cr1 0x0028 rw m pwm control register 1 0x 0000_00 00 mp 0 . cr2 0x002c rw m pwm control register 2 0x 0000_00 00 mp 0 . sr 0x003 0 r m pwm status register 0x 0000_00 00 mp 0 . ier 0x0034 rw m pwm interrupt enable 0x 0000_00 00 mp 0 . cnt 0x0038 r m pwm counter register 0x 0000_00 0 1 mp 0 . dtr 0x003c rw m pwm dead time control 0x 0000_00 0 0 mp 0 . pcr 0 0x0040 rw m pwm protection 0 control register 0x 00 00_00 00 mp 0 . psr 0 0x0044 rw m pwm protection 0 status register 0x 0000_00 80 mp 0 . p cr 1 0x0048 rw m pwm protection 1 control register 0x 0000_00 00 mp 0 . p sr 1 0x004c rw m pwm protection 1 status register 0x 0000_00 00 - 0x0054 - r eserved - mp 0 . atr 1 0x0058 rw m pwm a dc trigger reg 1 0x 0000_00 00 mp 0 . atr 2 0x005c rw m pwm adc trigger reg 2 0x 0000_00 00 mp 0 . atr 3 0x0060 rw m pwm adc trigger reg 3 0x 0000_00 00 mp 0 . atr 4 0x0064 rw m pwm adc trigger reg 4 0x 0000_00 00 mp 0 . atr 5 0x0068 rw m pwm adc trigger reg 5 0x 0000_00 00 mp 0 . atr 6 0x 006c rw m pwm adc trigger reg 6 0x0000_0000
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 154 mp 0 . mr mpwm mode register the pwm o peration m ode register is a 16 - bit register. mp0 . mr=0x4000 _ 4000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 motorb uao tup bup mchmod updown 0 0 0 0 00 0 rw rw rw rw rw rw 15 motorb 0 motor mode 1 normal mode 7 uao 0 update will be executed at designated timing. 1 update all duty, period register at once. when update set, duty and period registers are updated after two pwm clocks 5 tup 0 perio d, duty values are not updated at every period match. 1 period, duty values are updated at every period match. 4 bup 0 period, duty values are not updated at every bottom match 1 period, duty values are updated at every bottom match 2 1 mchmod 00 2 channels symmetric mode duty h decides toggle high/low time of h - ch duty l decides toggle high/low time of l - ch 01 1 channel asymmetric mode duty h decides toggle high time of h - ch duty l decides toggle low time of h - ch l channel become the inversion of h channel 10 1 channel symmetric mode duty h decides toggle high/low time of h - ch l channel become the inversion of h channel 11 not valid (same with 00) 0 updown 0 pwm up count mode (only available when motorb= 1 ) 1 pwm up/down count mode ( this bit should be 1 if motorb= 0 ) after initial pwm period and duty setting is completed, the uao bit should be set once for updating the setting value into the internal operating registers. this action will help to transfer the setting data from the user interface register to the internal operatin g register. the uao bit should stay at set state for at least 2 - pwm clock period s . otherwise, the update command can be missed and the internal registers will keep the previous data. mchmod in the mp0.mr fie ld is only effective when motorb in mp0.mr is a clear 0. otherwise , the mchmod field value will be ignored internally and will retain a 00 value. updown in the mp0.mr field is only effective when motorb in mp0.mr is set to 1. otherwise , the updown fi eld value will be ignored internally and will retain a 1 value. in the motor mode, the counter is always an up - down count operation.
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 155 mp 0 . olr mpwm output level register the pwm port mode register is a 16 - bit register. mp0 .olr =0x4000 _ 4004 7 6 5 4 3 2 1 0 whl vhl uhl wll vll ull 0 0 0 0 0 0 0 0 rw rw rw rw rw rw 5 whl 0 default level 1 inverted level 4 vhl 0 default level 1 inverted level 3 uhl 0 default level 1 inverted level 2 wll 0 default level 1 inverted level 1 vll 0 default level 1 inverted level 0 ull 0 default level 1 inverted level the normal level is defined in each operating mode as shown in table 15 . 3 . table 15 . 3 . mpwm register map pwm out put level normal mode motor mode up mode up down mode wh default level low high low active level high low high w l default level low low high active level high high low vh default level low high low active level high low high v l default level l ow low high active level high high low uh default level low high low active level high low high u l default level low low high active level high high low the polarity control block is shown in figure 15 . 2 . the example sho wn is for wh signal polarity control.
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 156 figure 15 . 2 . polarity control block mp 0 . f o l r mpwm force output level register the pwm force output register is an 8 - bit register. the pwm output level can be forced by an abnormal event occurring externally or from a user - intended condition. when the forced condition occurs, each pwm output level which is programmed in the folr register will be forced. mp0.folr=0x4000_4008 7 6 5 4 3 2 1 0 whfl vhfl uhfl wlfl vlfl ulfl 0 0 0 0 0 0 0 0 rw rw rw rw rw rw 5 whfl select wh output force level 0 1 output force level is l output force level is h 4 vhfl select vh output force level 0 1 output force level is l output force level is h 3 uhfl select uh output force level 0 1 output force level is l output force level is h 2 wlfl select wl output force level 0 1 output force level is l output force level is h 1 vlfl select vl output force level 0 1 output force level is l output force level is h 0 ulfl select ul output force level 0 1 output force level is l output force level is h
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 157 mp 0 . cr1 mpwm control register 1 the pwm c ontrol r egister 1 is a 16 - bit register. mp0 . cr1=0x4000_4028 15 14 13 12 11 1 0 9 8 7 6 5 4 3 2 1 0 irqn pwmen 000 0 0 0 0 0 0 0 rw rw 10 8 irqn irq interval number (every 1~8th prdirq,botirq,atrn) 0 pwmen pwm enable when this bit set 0, the pwm block stay in reset state but user interface can b e accessed. to operate the pwm block, this bit should be set 1. basically, prdirq and botirq are generated every period. however, the interrupt interval can be controlled from 0 to 8 periods. when irqn.cr1 = 0, the interrupt is requested every period ; ot herwise , the interrupt is requested every (irqn+1) times of period. mp 0 . cr2 mpwm control register 2 the pwm control r egister 2 is an 8 - bit register. mp0.cr2=0x4000_402c 7 6 5 4 3 2 1 0 halt pstart 0 0 0 0 0 0 0 0 rw rw 7 halt pwm halt (p wm counter stop but not reset) pwm outputs keep previous state 0 pstart 0 pwm counter stop and clear 1 pwm counter start (will be resynced @pwm clock twice) pwmen should be 1 to start pwm counter
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 158 mp 0 . prd mpwm period register the pwm p eriod r eg ister is a 16 - bit register. mp0 . prd=0x4000400c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 period 0x0002 rw 15 0 period 16 - bit pwm period. it should be larger than 0x0010 ( i f duty is 0x0000, pwm will not work) mp 0 . duh mpwm duty uh register the pwm u chan nel duty register is a 16 - bit register. mp0 . d u h=0x4000_4010 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 duty uh 0x0001 rw 15 0 duty uh 16 - bit pwm duty for uh output. it should be larger than 0x0001 ( i f duty is 0x0000, pwm will not work)
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 159 mp 0 . dvh mpwm du ty vh register the pwm v channel duty register is a 16 - bit register. mp0 .dvh =0x4000_4014 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 duty vh 0x0001 rw 15 0 duty vh 16 - bit pwm duty for vh output. it should be larger than 0x0001 ( i f duty is 0x0000, pwm will not work) mp 0 . dwh mpwm duty wh register the pwm w channel duty register is a 16 - bit register . mp0 . d w h=0x4000_4018 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 duty wh 0x0001 rw 15 0 duty wh 16 - bit pwm duty for wh output. it should be larger than 0x0001 ( i f duty is 0x0000, pwm will not work)
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 160 mp 0 . dul mpwm duty ul register the pwm u channel duty register is a 16 - bit register. mp0 . d u l=0x4000_401c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 duty ul 0x0001 rw 15 0 duty ul 16 - bit pwm duty for ul output. it should be larger than 0x0001 ( i f duty is 0x0000, pwm will not work) mp 0 . dvl mpwm duty vl register the pwm v channel duty register is a 16 - bit register. mp0 . d v l=0x4000_4020 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 duty vl 0x0001 rw 15 0 duty vl 16 - bit pwm duty for vl output. it should be larger than 0x0001 (if duty is 0x0000, pwm will not work)
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 161 mp 0 . dwl mpwm duty wl register the pwm w channel duty register is a 16 - bit register . mp0 . d w l=0x4000_4024 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 duty wl 0x 0001 rw 15 0 duty wl 16 - bit pwm duty for wl output. it should be larger than 0x0001 (if duty is 0x0000, pwm will not work) mp 0 . ier mpwm interrupt enable register the pwm interrupt enable register is an 8 - bit register. mp0.ier=0x4000_4034 7 6 5 4 3 2 1 0 prdien botien whie vhie uhie wlie vlie ulie 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw 7 prdien pwm counter p eriod i nterrupt enable 0 1 int errupt disable int errupt enable 6 botien pwm counter b ottom i nterrupt enable 0 1 int errupt disable int errupt enable 5 w hie atr6ie wh duty or atr6 match interrupt enable 0 1 int errupt disable int errupt enable 4 vhie atr5ie vh duty or atr5 match interrupt enable 0 1 int errupt disable int errupt enable 3 u hie atr4ie uh duty or atr4 match interrupt ena ble 0 1 int errupt disable int errupt enable 2 w lie atr3ie wl duty or atr3 match interrupt enable 0 1 int errupt disable int errupt enable 1 vlie atr2ie vl duty or atr2 match interrupt enable 0 1 int errupt disable int errupt enable 0 u lie atr1ie ul duty or atr1 match interrupt enable 0 1 int errupt disable int errupt enable
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 162 mp0.ier[5:0] control bits are shared by duty match interrupt event and adc trigger match interrupt event. when adc trigger mode is disabled, the interrupt is generated by the du ty match condition. in other case s , the interrupt is generated by the adc trigger counter match condition. the adc trigger mode is selected by the atmod bit field in the atrm register. mp 0 . sr mpwm status register the pwm status register is a 16 - bit regist er. mp0 . sr=0x4000 _ 4030 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 down irqcnt prdif botif dwhif atr6f dvhif atr5f duhif atr4f dwlif atr3f dvlif atr2f dulif atr1f 0 000 0 0 0 0 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw rw rw 15 down 0 current pwm coun t mode is up 1 current pwm count mode is down 14 12 irqcnt interrupt count number of period match (interval prdirq mode) 7 prdi f pwm p eriod i nterrupt flag (w rite 1 to clear flag rite 1 to clear flag rite 1 to clear flag rite 1 to clear flag rite 1 to clear flag rite 1 to clear flag rite 1 to clear flag rite 1 to clear flag
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 163 mp0.sr[5:0] status bits are shared by the duty match interrupt event and the adc trigger match interrupt event. when adc trigger mode is disabled, the interrupt is generated by the duty match condition . in other cases, the interrupt is generated by the adc trigger counter match condition. the adc trigger mode is selected by the atmod bit field in the atrm register. mp 0 . cnt mpwm counter register the pwm c ounter r egister is a 16 - bit read - only register. m p0 . cnt=0x4000 _ 403 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cnt 0x0000 rw cnt pwm c ounter v alue mp 0 . dtr mpwm dead time register the pwm dead time r egister is a 16 - bit register. mp0 . dtr=0x4000 _ 40 3c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dten pshrt dtclk dt 0 0 0 0 0 0 0 0 0x00 rw rw rw 15 dt en dead - time function enable 2 - channel symmetric mode does not support dead time function. it should be disabled in 2 channel symmetric mode. 0 1 disable dead - time function enable dead - time functio n 14 pshrt protect short condition th is function is effective only f o r 2 channel symmetric mode. for 1 channel mode, never activated on both h - side and l - side at same time. l - side is always opposite of h - side. 0 1 enable output short protection functi on. (turn off both output when both h - side and l - side are active.) disable output short protection function. 8 dtclk dead - time prescaler 0 1 dead time counter uses pwm clk/4 dead time counter uses pwm clk/ 16 7 0 dt dead time value (dead time setting makes output delay of low to high transition in normal polarity) 0x01 ~0xff : dead time
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 1 64 protect short condtion is only for internal pwm level, not for external pwm level. when the internal signal of h - side and l - side are the same high level, the prot ection short function operates to force both h - side and l - side to low level. mp 0 . pcr mpwm protection 0 , 1 c ontrol register the pwm p rotection c ontrol r egister is a 16 - bit register. mp0.pcr0=0x4000_4040,mp0.pcr1=0x4000_4048 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 prot 0 en prot 0 pol protd protie whprotm vhprotm uhprotm wlprotm vlprotm ulprotm 0 0 000 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw rw rw 15 prot0en enable protection input 0 1 4 prot0pol select protection input polarity 0: low - active 1: hi gh - active 10 8 p rotd protection input debounce 0 C C
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 165 mp 0 . psr mpwm protection 0 , 1 status register the pwm pro tection status r egister is a 16 - bit register. this register indicates which outputs are disabled. user s can set the output masks manually. when writing a value, if protkey is not written , the written values are ignored. mp0.psr0=0x4000_4044,mp0.psr1=0x4000 _404c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 protkey protif whprot vhprot uhprot wlprot vlprot ulprot - 0 0 0 0 0 0 0 wo rc rw rw rw rw rw rw 15 8 protkey protection clear access key to clear flags, write the key with protection flag (psr0 key is 0xca and psr1 key is 0xac ) writing without protkey prohibited . 7 protif protection interrupt status 0 1 no protection interrupt protection interrupt occurred 5 w hprot activate w - phase h - side protection flag 0 1 protection not occurred. protection o ccurred or protection output enabled 4 vhprot activate v - phase h - side protection flag 0 1 protection not occurred. protection occurred or protection output enabled 3 u hprot activate u - phase h - side protection flag 0 1 protection not occurred. protec tion occurred or protection output enabled 2 w lprot activate w - phase l - side protection flag 0 1 protection not occurred. protection occurred or protection output enabled 1 vlprot activate v - phase l - sid e protection flag 0 1 protection not occurred. protection occurred or protection output enabled 0 u lprot activate u - phase l - side protection flag 0 1 protection not occurred. protection occurred or protection output enabled if the proten bit in mp.pcr register is enabled, on any asserting signal o n the external protection pins, the pwm output is prohibited with output values defined in mp.folr register. additionally, u ser s can prohibit the output manually by writing the designated value into the mp.psr register.
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 166 mp 0 . atr m mpwm n adc trigger counte r m r egister mp 0 . atr 1 mpwm adc trigger counter 1 register mp 0 .a tr 2 mpwm adc trigger counter 2 register mp 0 . atr 3 mpwm adc trigger counter 3 register mp 0 . atr 4 mpwm adc trigger counter 4 register mp 0 . atr 5 mpwm adc trigger counter 5 register mp 0 . atr 6 mpw m adc trigger counter 6 register the pwm adc t rigger c ounter r egister is a 32 - bit register. mp0 . atr1=0x4000 _ 4058 mp0 . atr2=0x4000 _ 405c mp0 . atr3=0x4000 _ 4060 mp0 . atr4=0x4000 _ 4064 mp0 . atr5=0x4000 _ 4068 mp0 . atr6=0x4000 _ 406c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 atudt atmod atcnt 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 rw rw rw 19 atudt trigger register update mode 0 1 adc trigger value applied at period match event (at the same time with period and duty registers update) trigger register update mode when this bit set, written trigger register values are sent to trigger compare block after two pwm clocks (through synchronization logic) 17 16 atmod adc trigger mode register 00 01 10 00 adc trigger disable trigger out when up count match trigger out when down count match trigger out when up - down count match 15 0 at cnt adc trigger counter (it should be less than pwm period)
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 167 functional description the mpwm includes 3 channels, e ach of which controls a pair of outputs . in normal pwm mode, each channel runs independently. six pwm outputs can be generated. each pwm output is built with various settings. figure 15 . 3 shows the diagram for generating pwm. figure 15 . 3 . pwm output generation chain normal pwm up count mode timing in normal pwm mode, each channel runs independently. six pwm outputs can be generated. an example of the wav eform is shown in figure 15 . 4 . before pstart is activated, the pwm output stays at the default value l. when pstart is enabled, the period counter starts up count up to the mp0.prd count value. in the f irst period, the mpwm does n ot generate a pwm pulse. the pwm pulse is generated from the second period. the active level is d e rived at the start of the counter value during duty value time.
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 168 figure 15 . 4 . up c ount mode waveform (motorb=1, updown=0) normal pwm up/down count mode timing the basic operation of up/down count mode is the same as up count mode except the one period is twice that in up count mode. the default active level is opposite in a pair pwm ou tput. this output polarity can be controlled by the mp0.olr register. figure 15 . 5 . up/down count mode waveform (motorb=0, mchmod=0, updown=1) motor pwm 2 - channel symmetric mode t iming the motor pwm operation has three types of operating mode s C 2 - c hannel s y m metric mode, 1 - c hannel s ym m etric mode , and 1 - c hannel a sym m etric mode. figure 15 . 6 shows an example of a 2 - channel symmetric mode wave form.
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 169 figure 15 . 6 . 2 - c hannel symmetric mode waveform (motorb=0,mchmod=00) the default start level of both h - side and l - side is low. for the h - side, pwm ouput level is changed to active level when the duty level is matched in up count period and is returned to the default level when the duty level is matched in down count period. the symmetrical feature appears in each channel which is controlled by the corresponding duty register value. motor pwm 1 - channel asymmetric mode timing the 1 channel asymmetric mode makes asymmetric duration pulses which are defined by the h - side and l - side duty register. therefore, the l - side signal is always the negative signal of the h - side. during up count period, the h - side duty register matching condition generates the active level pulse and during down count period, the l - side duty register matiching condition generates the default level pulse. figure 15 . 7 . 1 - channel asymmetric mode waveform (motorb=0,mchmod=01)
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 170 the default start level of both h - side and l - side is low. for the h - side, pwm ouput level is changed to active level when the h - side duty level is matched in up count period and is returned to the default level when the l - side duty level is matched in down count period. when the pstart is set, the l - side pwm output is changed to the active level , then the l - side pwm output is the inverse output of the h - side output. motor pwm 1 - chan nel symmetric mode timing the 1 - channel symmetric mode generates a symmetric duration pulse which is defined by the h - side duty register. therefore, the l - side signal is always the negative signal of h - side. during up count period, the h - side duty register matching condition generates the active level pulse and during down count period, the h - side duty register matiching condition also generates the default level pulse. figure 15 . 8 . 1 - channel symmetric mode waveform (motorb=0,mchmod=10) the default start level of both h - side and l - side is low. for the h - side, pwm ouput level is changed to active level when the h - side duty level is matched in up count period and is returned to the d efault level when the h - side duty level is matched again in down count period. when the pstart is set, the l - side pwm output is changed to the active level , then the l - side pwm output is the inverse output of h - side output. pwm dead - time operation to prev ent an external short condition, the mpwm provides a dead - time function. this function is only available in the motor pwm mode. when either theh - side or l - side output changes to active level, an amount of dead - time is inserted if the dten.mp.dtr bit is ena bled. the duration of dead - time is decided by the value in the dt.mp.dtr[7:0] field. when dtclk = 0, the dead - time duration = dt[7:0] * (pwm clock period * 4) when dtclk = 1, the dead - time duration = dt[7:0] * (pwm clock period * 16) when t he pwm counter r eaches the duty value, the pwm output is masked and the dead - time counter starts to run. when the dead - time counter reache s the value in the dt[7:0] register, the output mask is disabled.
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 171 figure 15 . 9 is an example of dead - time ope ration in 1 channel symmetric mode. figure 15 . 9 . pwm dead - time operation timing diagram (symmetric mode) figure 15 . 10 display s an example of dead - time o peration in 1 - channel asymmetric mode. figure 15 . 10 . pwm dead - t ime operation t iming d iagram ( as ymmetric m ode) the dead - time function is not available for 2 - channel symmetric mode . therefore, the dead condition is generated by each channels duty control. mpwm dead - time timing examples for special conditions figure 15 . 11 shows the operation of dead - time. in normal dead - time, dead - time masking is activated at duty match time and the dead - time counter runs. when the dead - time counter reaches the dead time value, the mask is disabled. mp.dul/v/w mp.d uh/v/w mp0uh mp0vh mp0wh mp0uh mp0vh mp0wh mp.cnt mp.dtr mp.dtr mp.duh/v/w mp0uh mp0vh mp0wh mp0uh mp0vh mp0wh mp.cnt mp.dtr mp.dtr
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 172 figure 15 . 11 . normal dead - t ime operation (t duty >t dt ) the following figures display special - case scenarios of dead time configurations. figure 15 . 12 . minimum h - side pulse timing (t duty z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 173 figure 15 . 13 . zero h - side p ulse t iming (t dt >2xt duty ) figure 15 . 14 . minimum l - s ide p ulse t iming (t dt z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 174 figure 15 . 15 . zero l - side p ulse t iming (t dt >period - t duty ) figure 15 . 16 . h - s ide a lways o n (t duty =period: d ead - t ime d i sabled) mp.dxh=0 mp.cnt mp0uh mp0vh mp0wh mp0uh mp0vh mp0w h mp.prd no rising mas k no falling mask always h always l dt - rising mask dt - falling mask masked masked masked mp.duh/v/w mp0uh mp0vh mp0wh mp0uh mp0vh mp0wh mp.cnt t dt - rising t dt - falling t dt - falling 2 x t duty dt - rising mask dt - falling mask mp.prd
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 175 figure 15 . 17 . l - s ide a lways o n (t duty =0: dead - time d isabled) symmetrical mode vs asymmetrical mode in symmetrical mode, the waveform is symmetrical on both sides of th e mid - point of the period . the duty comparison is performed twice in both up and down count period. figure 15 . 18 . symmetrical pwm timing mp.duh/v/w mp0vh mp0vl mpxcnt mp0wh mp0wl mp0uh mp0ul mp.dul/v/w data cannot be acquired mp.dxh=mp.prd mp.cnt mp0uh mp0vh mp0wh mp0uh mp0vh mp0wh dt - rising mask dt - falling mask mp.prd no rising mask no falling mask always l always h
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 176 in asymmetrical mode, the waveform is not symmetrical from the mid - point of the period. the duty comparison of h - side is performed in both up count period . the duty comparison of l - side is performed in both down count period. figure 15 . 19 . asymm etrical pwm timing and sensing m argin adc triggering function six adc trigger timing registers are provided. this dedicated register creates a trigger signal to start the adc conversion. the conversion channel of adc is defined in the adc control register. figure 15 . 20 . adc triggering f unction t iming d iagram adc0_st adc1_st pwm_v pwm_w pwm_u adc_int ? max. 6 adc triggering timing (mp.atr1~mp.atr6) ? mp.atr registers are set by indipendently from the duty settings. mp.atr2 mp.cnt mp.prd mp.atr1 mp.dul mp.duh mp0vh mp0vl mp.cnt mp0wh mp0wl mp0uh mp0ul mp.dvh sensing margin mp.dvl mp.dwh/dwl
z32f064 1 p roduct specification motor pulse widt h modulator ps03440 4 - 0417 preliminary 177 figure 15 . 21 shows an example of adc data acquisition. figure 15 . 21 . an example of adc aquisition timing by event from mpwm interrupt generation timing each timing event can make an interrupt request to the cpu. mp.duh mp0v h mp0vl mp.cnt mp0w h mp0wl mp0u h mp0ul mp.dvh adc start (mpxatr1==mpxcnt) mp.dwh adc sta rt mp.atr1 adc d ma tran sfer ia, ib
z32f064 1 p roduct specification motor pulse width modulator ps03440 4 - 0417 preliminary 178 figure 15 . 22 . interrupt generation timing
z32f064 1 product specification 12 - bit a/d converter ps03440 4 - 0417 preliminary 179 16. 12 - b it a/d c onverter introduction the a / d converter (adc) block consists of two independent adc units . features include: ? 11 c hannel s of analog inputs (each adc has 8 input channels) ? single and continuous conversion mode ? up to 8 times sequential conversion support s ? software trigger support s ? 4 internal trigger sources support s (pwms, timers) ? adjustable sample and hold time ? dma transfers figure 16 . 1 block diagram adc control ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 12 - bit sar adc0 soc eoc pd chsel stsel ad c data0 adc data1 adc data2 adc data3 adc data4 adc data5 adc data6 adc data7 trigger control interrupt control timers mpwm adc irq channel selection s/h apb bus
z32f064 1 product specification 12 - bit a/d converter ps03440 4 - 0417 preliminary 180 pin d escription table 16 . 1 external signal pin name t ype d escription vdd p analog power( 3.0v~ 5v ) vss p analog gnd an0 a adc input 0 an1 a adc input 1 an2 a adc input 2 an3 a adc input 3 an4 a adc input 4 an5 a adc input 5 an6 a adc input 6 an7 a adc input 7 an8 a adc input 8 an9 a adc input 9 an10 a adc input 10 r egisters the b ase addresses of the adc units are shown in table 16 . 2 . table 16 . 2 adc base a ddress n ame base address adc 0 0x4000_ b 000 adc 1 0x4000_b 1 00
z32f064 1 product specification 12 - bit a/d converter ps03440 4 - 0417 preliminary 181 table 16 . 3 adc register m ap n ame o ffset t ype d escription rese t value adn . m r 0x0000 rw adc mode register 0x00 adn . cs c r 0x0004 rw adc current sequence/ channel register 0x00 adn . c c r 0x0008 rw adc clock control register 0x80 adn . t rg 0x000c rw adc trigger selection register 0x00 - 0x0010 - r eserved - 0x0014 - r ese rved adn . s cs r 0x0018 rw adc burst mode channel select 0x00 adn . cr 0x0020 rw adc control register 0x00 adn . s r 0x0024 rw adc status register 0x00 adn . ie r 0x0028 rw adc interrupt enable register 0x00 ad n . d d r 0x002c r adc n dma data r egister 0x00 ad n . dr 0 0x0030 r adc n sequence 0 data register 0x00 ad n . d r 1 0x0034 r adc n sequence 1 data register 0x00 ad n . d r 2 0x0038 r adc n sequence 2 data register 0x00 ad n . dr 3 0x003c r adc n sequence 3 data register 0x00 ad n . dr 4 0x0040 r adc n sequence 4 data register 0x0 0 ad n . dr5 0x0044 r adc n sequence 5 data register 0x00 ad n . dr 6 0x0048 r adc n sequence 6 data register 0x00 ad n . dr 7 0x004c r adc n sequence 7 data register 0x00
z32f064 1 product specification 12 - bit a/d converter ps03440 4 - 0417 preliminary 1 82 ad n . mr adc n mode register the adc mode r egisters are 32 - bit registers. this register configu res adc o peration mode . this register configures the adc operation mode and should be written first before the other adc registers are written. ad0 . mr=0x4000_b000, ad1 . mr=0x4000_b100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dmaen dmach stsel seqcnt aden arst admod trgsel 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 rw rw rw rw rw rw rw rw 17 dmaen dma enable bit C
z32f064 1 product specification 12 - bit a/d converter ps03440 4 - 0417 preliminary 183 if adcmod is set for burst mode, the adc channels are controlled by seq 0ch ~ seq 7ch. sequential m ode always start s from seq 0ch.(in 3 sequential mode, analog inputs of channels which are assigned at seq 0ch , seq 1ch , and seq 2ch are converted sequentially) . figure 16 . 2 analog channel block diagram ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch0 ch1 ch2 c h3 ch4 ch5 ch6 ch7 an0 an1 an2 an3 an4 an8 an9 an10 an5 an6 an7 adc0 adc1 adout[11:0] adout[11:0]
z32f064 1 product specification 12 - bit a/d converter ps03440 4 - 0417 preliminary 184 ad n . cscr adc n c urrent sequence/c hannel register adc current sequ e n ce/channel r egisters are 7 - bit registers. this register consist s of current sequence numbers ( cseqn ) and curren t active channel val ues. cseqn can be written to set the current sequence number imme diat e ly. this register s hould be written first before adn . scsr is written. ad0. c s c r=0x4000_b004, ad1. c s c r=0x4000_b104 7 6 5 4 3 2 1 0 cseqn cach 0x0 0x0 rw ro 7 4 cseqn current seque nce number , can write when not abusy 0000 current sequence is 0 0001 current sequence is 1 0010 current sequence is 2 0011 current sequence is 3 0100 current sequence is 4 0101 current sequence is 5 0110 current sequence is 6 0111 current sequence is 7 3 0 cach current active channel 0000 adc channel 0 is active 0001 adc channel 1 is active 0010 adc channel 2 is active 0011 adc channel 3 is active 0100 adc channel 4 is active 0101 adc channel 5 is active 0110 adc channel 6 is active 0111 adc channel 7 is active 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved
z32f064 1 product specification 12 - bit a/d converter ps03440 4 - 0417 preliminary 185 ad n . ccr adc n clock control register adc control registers ar e 16 - bit registers. ad0.c c r1=0x4000_b008, ad1.c c r1=0x4000_b108 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 adcpda c l kdiv adcpd extclk clkinvt 0 0x00 1 0 0 rw rw rw rw rw 15 adcpda adc r - dac disable to save power dont set 1 here(its opti C C C C C C
z32f064 1 product specification 12 - bit a/d converter ps03440 4 - 0417 preliminary 186 ad n . trg adc t rigger selection register the adc trigger registers are 32 - b i t registers. in single/ burst m ode, all the bit fields are used. in burst c onversion mode, o nly the bst trg bit field (bit3~bit0) is used. ad0.trg=0x4000_b00c, ad1.trg=0x4000_b10c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 seqtrg7 seqtrg6 seqtrg5 seqtrg4 seqtrg3 seqtrg2 seqtrg1 seqtrg0 bsttrg 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 rw rw rw rw rw rw rw rw 3 0 28 seqtrg7 8 th sequence trigger source 2 6 2 4 seqtrg6 7 th sequence trigger source 2 2 20 seqtrg5 6 th sequence trigger source 1 8 16 seqtrg4 5 th sequence trigger source 1 4 12 seqtrg3 4 th sequence trigger source 1 0 8 seqtrg2 3 rd sequence trigger source 6 4 seqtrg1 2 nd sequence trigger source 2 0 s eqtrg0 bsttrg 1 st sequence trigger source burst conversion trigger source value timer (trgsel 2 h1) mpwm0 (trgsel 2 h2) 0 timer 0 mp0atr1 1 timer 1 mp0atr2 2 timer 2 mp0atr3 3 timer 3 mp0atr4 4 timer 8 mp0atr5 5 timer 9 mp0atr6 6 - bottom 7 - period
z32f064 1 product specification 12 - bit a/d converter ps03440 4 - 0417 preliminary 187 ad n . scsr adc sequence channel selection register the adc burst mode channel select register is a 32 - bit register. ad0. sc sr=0x4000_b018, ad1. s csr=0x4000_b118 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 seq7ch seq6ch seq5ch seq4ch seq3ch seq2ch seq1ch seq0ch 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 rw rw rw rw rw rw rw rw 31 28 seq7ch 8 th conversion sequence channel selection 27 24 seq6ch 7 th conversion sequence channel selection 23 20 seq5ch 6 th conversion sequence channel selection 19 16 seq4ch 5 th c onversion sequence channel selection 15 12 seq3ch 4 th conversion sequence channel selection 11 8 seq2ch 3 rd conversion sequence channel selection 7 4 seq1ch 2 nd conversion sequence channel selection 3 0 seq 0ch 1 st conversion sequence channel selection this channel should be used for single mode
z32f064 1 product specification 1 2 - bit a/d converter ps03440 4 - 0417 preliminary 188 ad n . cr adcn control register the adcn control r egister controls start or stop adc conversion operations. this r egister is an 8 - bit register. ad0.cr=0x4000_b020, ad1.cr=0x4000_b120 7 6 5 4 3 2 1 0 astop astart 0 0 w rw 7 astop 0 no 1 adc conversion stop (will be clear next @adc clock) if astop set after conversion cycle start, present conversion would be completed. 0 astart 0 no adc c onversion 1 adc conversion start (will be clear next @adc clock) adcen should be 1 to start adc if astart is set as 1 h1 when arst is 1 h0 in trigger event mode, adc conversion will start once as seqcnt set. ad n . sr adc n status register the adc sta tus register is a 32 - bit register. ad0.sr=0x4000_b024, ad1.sr=0x4000_b124 7 6 5 4 3 2 1 0 eoc abusy dovrun dmairq trgirq eosirq - eocirq 0 0 0 0 0 0 - 0 ro ro ro ro rc rc - rc 7 eoc adc end - of - c onversion flag ( start - of - conversion made by adc_clk cle ars this bit , not astart ) 6 abusy adc conversion busy flag 5 dovrun dma overrun flag (not interrupt) (dma ack didnt come until end of next conversion) e 1 to clear flag write 1 to clear flag write 1
z32f064 1 product specification 12 - bit a/d converter ps03440 4 - 0417 preliminary 189 ad n . ier interrupt enable register four interrupts are provided for adc oper ations. each interrupt can be enabled by writing 1 to the corresponding bit in the adn.ier register. ad0.ier=0x4000_b028, ad1.ier=0x4000_b128 7 6 5 4 3 2 1 0 dmairqe trgirqe eosirqe eocirqe 0 0 0 0 rw rw rw rw 4 d ma i rq e dma done interru pt enable 0: int errupt disable 1: int errupt enable 3 t rg i rq e adc trigger conversion interrupt enable 2 eosirqe adc sequence conversion interrupt enable 0 eocirqe adc single conversion interrupt enable
z32f064 1 product specification 12 - bit a/d converter ps03440 4 - 0417 preliminary 190 ad n . ddr adc n dma data register the adc dma data register is a 16 - bit register. this register is a temporary register only for dma transfer (a / d conversion data of just completed conversion) . ad0.ddr=0x4000_b02c, ad1.ddr=0x4000_b12c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 adc dma temporary data adm ach 0x000 0x0 r r 15 4 addmar adc conversion result data (12 - bit) 3 0 admach adc data channel indicator ad n . dr adc n sequence data register 0~7 adc data registers are 16 - bit registers holding the adc conversion from the result register. ad0.dr0=0x4 000_b030, ad0.dr1=0x4000_b034, ad0.dr2=0x4000_b038, ad0.dr3=0x4000_b03c ad0.dr4=0x4000_b040, ad0.dr5=0x4000_b044, ad0.dr6=0x4000_b048, ad0.dr7=0x4000_b04c ad1.dr0=0x4000_b130, ad1.dr1=0x4000_b134, ad1.dr2=0x4000_b138, ad1.dr3=0x4000_b13c ad1.dr4=0x4000_b14 0, ad1.dr5=0x4000_b144, ad1.dr6=0x4000_b148, ad1.dr7=0x4000_b14c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 adcdata 0x000 r 15 4 adc data adc channel 0~ 7 data (12 - bit)
z32f064 1 product specification 12 - bit a/d converter ps03440 4 - 0417 preliminary 191 functional description adc single mode timing adc conversion is started when adcn.cr.astart is written as 1 in single conversion mode. after adcncr.astart is set, start of conversion (s o c) will be activated in 3 adc clocks, adcn.sr.eocirq will be set in 2 adc clocks, and 2 pclks after the end of conversion . figure 16 . 3 . adc single m ode t iming ( when adcn.mr.amod = 0) adc sequential mode timing diagram there are two sou rces to start conversion in burst mode: C trg event (timer and mpwm) and astart . when trgsel is set as the timer event trigger or mpwm event trigger, the conversion is started by the trigger of adn.trg.bsttrg (and.trg[3:0]). for example, adc conversion will be started by the trigger of timer9 if adn.trg.bsttrg is set as timer9. once the bsttrgs trigger events occur, the adc will convert all channels defined in sequence (and.mr.seqcnt contains the number of channels to convert). see figure 16 . 5 . figure 16 . 4 . adc burst mode timing ( w hen adcn.mr.amod = 1 )
z32f064 1 product specification 12 - bit a/d converter ps03440 4 - 0417 preliminary 192 figure 16 . 5 . adc trigger t iming in burst m ode (seqcnt = 3b111, 8 sequence c o n version ) adc sequential conversion mode timing diagram to set sequential conversion mode, adn.mr.amod is 2b00 and adn.mr.seqcnt is not 2b00. the o peration of sequential mode is almost the same as burst mode. the difference is th e source of soc. each soc is ma de by the trigger of the seqtrgx as each seqcnt. see figure 16 . 7 . figure 16 . 6 . adc sequential m ode t iming ( w hen adn.mr.amod = 0 and adn.mr.seqcnt
z32f064 1 product specification 12 - bit a/d converter ps03440 4 - 0417 preliminary 193 figure 16 . 7 . adc t rigger t iming in sequential m ode (seqcnt = 3b111, 8 s equence c o n version)
z32f064 1 product specification electrical characteristics ps03440 4 - 0417 preliminary 194 17. electrical characteristic s dc characteristics absolute maximum ratings absolute maximum ratings are limiting values of operating and environmental conditions which should not be exceeded under the worst possible conditions . table 17 . 1 absolute m aximum r ating s parameter symbol m in m ax u ni t power supply (vdd) vdd - 0.5 + 6 v analog power supply (avdd) avdd - 0.5 + 6 v vdc output voltage vdd18 v input high voltage - vdd+0.5 v input low voltage vss C 0.5 - v output low current per pin i ol 2.5 ma output low current total i ol 25 ma output high current per pin i oh C 2.5 ma output low current total i o h 25 ma input main clock range 0.4 8 mhz operating frequency - 48 mhz storage temperature t st - 55 +125 operating temperature t op - 40 + 85
z32f064 1 product specification electrical characteristics ps03440 4 - 0417 preliminary 195 dc characteristics table 17 . 2 recommended operating condition s parameter symbol condition min typ ical max u nit supply voltage vdd 3 . 0 5.5 v supply voltage avdd 3 . 0 5.0 5.5 v operating frequency freq mosc 4 8 mhz intosc 1 mhz pll 4 80 mhz operating temperature top top - 40 + 85 table 17 . 3 dc electrical characteristics (vdd = +5v, ta = 25 ) parameter symbol condition min typ ical max u nit input low voltage vil schmitt input - - 0. 2 vdd v input high voltage vih schmitt input 0. 8 vd d - - v output low voltage vol iol = 10ma - - vss+ 1 v output high voltage voh ioh = - 3 ma vdd C 1 - - v output low current iol - - 3 ma output high current ioh - 3 - ma input high leakage iih 4 ua input low leakage iil - 4 pull - up resister rpu rmax:vdd= 3 . 0 v rmin:vdd=5v 30 - 70 k
z32f064 1 product specification electrical characteristics ps03440 4 - 0417 preliminary 196 current consumption table 17 . 4 . current c onsumption in e ach m ode ( temperature: +25 ) parameter symbol condition min typ ical max u nit normal operation idd normal rosc=run mxosc=8mhz hclk= 48 mhz 20 20 - ma sleep mode idd sleep rosc=run mxosc=stop hclk = 48 mhz - 8.3 - m a note: uart en, 1 port toggle @5v por electrical characteristics table 17 . 5 por electrical characteristics ( temperature: - 40 ~ + 85 ) parameter symbol condition min typ ical max u nit operating voltage vdd 18 1.6 1.8 2.0 v operating current idd por t yp. <6ua i f always on - 60 - na por set level vr por vdd rising (slow) 1.3 1.4 1.55 v por reset level vf por vdd falling (slow) 1.1 1.2 1.4 v
z32f064 1 product specification electrical characteristics ps03440 4 - 0417 preliminary 197 lvd el ectrical characteristics table 17 . 6 . lvd electrical characteristics ( temperature: - 40 ~ + 85 ) parameter symbol condition min typ ical max u nit operating voltage vdd 1.7 5 v operating current idd lvd t yp. <6ua when always on - 1 - m a lvd set level 0 v lvd 0 vdd falling (slow) 1. 6 1.8 2 . 0 v lvd set level 1 v lvd 1 vdd falling (slow) 2. 0 2.2 2. 5 v lvd set level 2 v lvd 2 vdd falling (slow) 2.5 2 . 7 3. 0 v lvd set level 3 v lvd 3 vdd falling (slow) 3 . 9 4.3 4. 6 v vdc electrical characteristics table 17 . 7 vdc electrical characteristics ( temperature: - 40 ~ + 8 5 ) parameter symbol condition min typ ical max u nit operating voltage vdd vdc 3 . 0 - 5.5 v vdc output voltage vout vdc @run 1.62 1.8 1.98 v @stop 1.4 1.8 2.0 v regulation current i out 100 ma drop - out voltage vdrop vdc vddvdc= 3 . 0 v iout=100ma - - 200 m v current consumption idd norm @run - 100 150 ua idd stop @stop - 1 2 ua
z32f064 1 product specification electrical characteristics ps03440 4 - 0417 preliminary 198 external osc characteristics table 17 . 8 external osc characteristics ( temperature: - 40 ~ + 85 ) parameter symbol condition min typ m ax u nit operating voltage vdd 3 . 0 - 5.5 v idd @4mhz/5v - 240 ua frequency oscf req 4 8 10 mhz output voltage osc vout 1.2 2.4 - v load capacitance load cap 5 22 35 pf pll electrical characteristics table 17 . 9 pll electrical characteristics ( temperature: - 40 ~ + 85 ) parameter symbol condition min typ. max u nit operating voltage vdd pll 3.0 5.5 v output frequency fout 4 48 mhz operating current idd pll @ 5 0mhz 1.3 ma duty fout duty 40 - 60 % p - p jitter jitter @lock 500 p s vco vco 2 0 80 mhz input freque ncy fin 4 8 mhz locking time lock 1 ms
z32f064 1 product specification electrical characteristics ps03440 4 - 0417 preliminary 199 adc electrical characteristics table 17 . 10 . adc electrical characteristics ( temperature: - 40 ~ + 85 operating v oltage a vdd 3.0 5 5. 5 v reference voltage avref 3.0 5 5. 5 v resolution 12 bit operating current idda 2.8 ma analog input range 0 avdd v conversion rate - 1 . 6 m sps operating frequency aclk 25 mhz dc accuracy inl 2.5 lsb dnl 1.0 lsb offset error 1.5 lsb full scale error 1.5 lsb sndr sndr 68 db thd - 70 db dn l : maximum deviation between actual steps and the ideal one. inl : integral linearity error: maximum deviation between any actual transition and the end point
z32f064 1 product specification package ps03440 4 - 0417 preliminary 200 18. package figure 18 . 1 displays the lqfp - 48 package dimension and figure 18 . 2 shows the lqfp - 32 package dimension. l qfp - 48 package figure 18 . 1 package d imension ( l qfp - 48 7 x 7 ) note : all dimensions refer to jedec standard ms - 026 bdd do not include mold flash or protrusions .
z32f064 1 product specification package ps03440 4 - 0417 preliminary 201 l qfp - 32 package figure 18 . 2 package d imension ( l qfp - 32 7 x 7 ) note : all dimens ions refer to jedec standard ms - 026 bdd do not include mold flash or protrusions . all dimensions refer to jedec standard ms - 026 bdd do not include mold flash or protrusions
z32f064 1 product specification ordering information ps03440 4 - 0417 preliminary 202 19. ordering information table 19 . 1 identifies the basic features and package styles available for the z32f064 1 mcu. table 19 . 1 o rdering information for the z32f064 1 mcu device flash size sram uart spi i 2 c mpwm adc i/o por ts package z32f06410aes 64 kb 8 kb 2 1 1 1 2 - unit 11 channel 44 lqfp - 48 Z32F06410AKS 64 kb 8 kb 2 1 1 1 2 - unit 8 channel 30 lqfp - 32 zilog part numbers consist of a number of components , which are described below using part number z32f06410aes as an exa mple.

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